From 4731b1f73e0bfe3e3539f6b7c17e0f5366996a98 Mon Sep 17 00:00:00 2001 From: "neeraj.dantu" Date: Sun, 21 Nov 2021 23:26:05 -0600 Subject: [PATCH 1/2] Add OSD32MP1-BRK device tree support Signed-off-by: Kory Maincent --- arch/arm/dts/Makefile | 3 +- .../dts/stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi | 119 ++ .../dts/stm32mp157c-osd32mp1-brk-u-boot.dtsi | 219 ++++ arch/arm/dts/stm32mp157c-osd32mp1-brk.dts | 1120 +++++++++++++++++ 4 files changed, 1460 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi create mode 100644 arch/arm/dts/stm32mp157c-osd32mp1-brk-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-osd32mp1-brk.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83677c3d4f..6e67c6d18a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -959,7 +959,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157f-ed1.dtb \ stm32mp157f-ev1.dtb \ stm32mp15xx-dhcom-pdk2.dtb \ - stm32mp15xx-dhcor-avenger96.dtb + stm32mp15xx-dhcor-avenger96.dtb \ + stm32mp157c-osd32mp1-brk.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi b/arch/arm/dts/stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi new file mode 100644 index 0000000000..362f3281b8 --- /dev/null +++ b/arch/arm/dts/stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + * + */ + +/* + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs + * DDR type: DDR3 / DDR3L + * DDR width: 16bits + * DDR density: 4Gb + * System frequency: 533000Khz + * Relaxed Timing Mode: false + * Address mapping type: RBC + * + * Save Date: 2020.08.20, save Time: 10:57:25 + */ + +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00041401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00070707 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x1F000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x06060606 +#define DDR_ADDRMAP6 0x0F060606 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE80 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE80 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 diff --git a/arch/arm/dts/stm32mp157c-osd32mp1-brk-u-boot.dtsi b/arch/arm/dts/stm32mp157c-osd32mp1-brk-u-boot.dtsi new file mode 100644 index 0000000000..b7284f3028 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-osd32mp1-brk-u-boot.dtsi @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/ +/* + * Copyright (C) 2020, Octavo Systems LLC - All Rights Reserved + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +#include +#include "stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi" +#include "stm32mp15-u-boot.dtsi" +#include "stm32mp15-ddr.dtsi" + + +/ { + + aliases{ + i2c0 = &i2c4; + mmc0 = &sdmmc1; + usb0 = &usbotg_hs; + }; + + config{ + u-boot,boot-led = "LED2_GRN"; + u-boot,error-led = "LED2_RED"; + u-boot,mmc-env-partition = "fip"; + st,stm32prog-gpios = <&gpiod 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + +#ifdef CONFIG_STM32MP15x_STM32IMAGE + config { + u-boot,mmc-env-partition = "ssbl"; + }; + + /* only needed for boot with TF-A, witout FIP support */ + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x02000000>; + no-map; + }; + }; +#endif + +}; /*root*/ + +#ifndef CONFIG_TFABOOT + +&clk_hse { + st,digbypass; +}; + +&rcc { + u-boot,dm-pre-reloc; + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + pll2:st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + pll3:st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + pll4:st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; + +&i2c4{ + u-boot,dm-pre-reloc; +}; + +&i2c4_pins_z_mx { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc1{ + u-boot,dm-pre-reloc; +}; + +&sdmmc1_pins_mx { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +#endif /*CONFIG_TFABOOT*/ + +&cryp1{ + u-boot,dm-pre-reloc; +}; + +&hash1{ + u-boot,dm-pre-reloc; +}; + +&uart4{ + u-boot,dm-pre-reloc; +}; + +&usbotg_hs{ + u-boot,dm-pre-reloc; + u-boot,force-b-session-valid; + hnp-srp-disable; + dr_mode = "peripheral"; +}; + +&usbphyc{ + u-boot,dm-pre-reloc; +}; + +&usbphyc_port0{ + u-boot,dm-pre-reloc; +}; + +&usbphyc_port1{ + u-boot,dm-pre-reloc; +}; + +&adc{ + status = "okay"; +}; + +#ifndef CONFIG_STM32MP1_TRUSTED +&i2s2{ + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +}; + +&pmic{ + u-boot,dm-pre-reloc; +}; + +&sai2{ + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; +}; +#endif /*CONFIG_STM32MP1_TRUSTED*/ diff --git a/arch/arm/dts/stm32mp157c-osd32mp1-brk.dts b/arch/arm/dts/stm32mp157c-osd32mp1-brk.dts new file mode 100644 index 0000000000..d5f2793f54 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-osd32mp1-brk.dts @@ -0,0 +1,1120 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) Octavo Systems LLC 2020 - All Rights Reserved + */ + +/* For more information on Device Tree configuration, please refer to + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration + */ + +/dts-v1/; +#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15-m4-srm.dtsi" +#include +#include +#include + +/ { + model = "Octavo OSD32MP1 BRK board"; + compatible = "st,stm32mp157c-osd32mp1-brk", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2:mcuram2@10000000{ + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0:vdev0vring0@10040000{ + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1:vdev0vring1@10041000{ + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer:vdev0buffer@10042000{ + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram:mcuram@30000000{ + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram:retram@38000000{ + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved:gpu@d4000000{ + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + + led{ + compatible = "gpio-leds"; + + red1{ + label = "LED1_RED"; + gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + status = "okay"; + default-state = "off"; + }; + + green1{ + label = "LED1_GRN"; + gpios = <&gpioz 7 GPIO_ACTIVE_LOW>; + status = "okay"; + default-state = "on"; + }; + + red2{ + label = "LED2_RED"; + gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + status = "okay"; + default-state = "off"; + }; + + green2{ + label = "LED2_GRN"; + gpios = <&gpioi 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + usb_phy_tuning:usb-phy-tuning{ + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; + + vin:vin{ + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + aliases{ + serial0 = &uart4; + serial2 = &usart2; + serial5 = &uart5; + serial7 = &uart7; + serial1 = &uart8; + }; + + chosen{ + stdout-path = "serial0:115200n8"; + }; + +}; /*root*/ + +&pinctrl { + u-boot,dm-pre-reloc; + i2c1_pins_mx: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_pins_sleep_mx: i2c1-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c2_pins_mx: i2c2-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_mx: i2c2-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + i2c5_pins_mx: i2c5-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_pins_sleep_mx: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + spi2_pins_mx: spi2-0 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_sleep_pins_mx: spi2-sleep-0 { + pins { + pinmux = , /* SPI2_SCK */ + , /* SPI2_MISO */ + ; /* SPI2_MOSI */ + }; + }; + + spi4_pins_mx: spi4-0 { + pins1 { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + + spi4_sleep_pins_mx: spi4-sleep-0 { + pins { + pinmux = , /* SPI2_SCK */ + , /* SPI2_MISO */ + ; /* SPI2_MOSI */ + }; + }; + + usart2_pins_mx: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_mx: usart2-idle-0 { + pins1 { + pinmux = ; /* USART2_TX */ + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_mx: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; + + uart5_pins_mx: uart5-0 { + pins1 { + pinmux = ; /* USART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART5_RX */ + bias-disable; + }; + }; + + uart5_idle_pins_mx: uart5-idle-0 { + pins1 { + pinmux = ; /* USART5_TX */ + }; + pins2 { + pinmux = ; /* USART5_RX */ + bias-disable; + }; + }; + + uart5_sleep_pins_mx: uart5-sleep-0 { + pins { + pinmux = , /* USART5_TX */ + ; /* USART5_RX */ + }; + }; + + uart7_pins_mx: uart7-0 { + pins1 { + pinmux = ; /* USART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART7_RX */ + bias-disable; + }; + }; + + uart7_idle_pins_mx: uart7-idle-0 { + pins1 { + pinmux = ; /* USART7_TX */ + }; + pins2 { + pinmux = ; /* USART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_mx: uart7-sleep-0 { + pins { + pinmux = , /* USART7_TX */ + ; /* USART7_RX */ + }; + }; + + uart8_pins_mx: uart8-0 { + pins1 { + pinmux = ; /* USART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART8_RX */ + bias-disable; + }; + }; + + uart8_idle_pins_mx: uart8-idle-0 { + pins1 { + pinmux = ; /* USART8_TX */ + }; + pins2 { + pinmux = ; /* USART8_RX */ + bias-disable; + }; + }; + + uart8_sleep_pins_mx: uart8-sleep-0 { + pins { + pinmux = , /* USART8_TX */ + ; /* USART8_RX */ + }; + }; + + m_can1_pins_mx: m-can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_mx: m_can1-sleep@0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + pwm1_pins_mx: pwm1-0 { + pins { + pinmux = ; /* TIM1_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_mx: pwm1-sleep-0 { + pins { + pinmux = ; /* TIM1_CH1 */ + }; + }; + + pwm3_pins_mx: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_mx: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + + pwm4_pins_mx: pwm4-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_mx: pwm4-sleep-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_mx: pwm8-0 { + pins { + pinmux = ; /* TIM8_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_mx: pwm8-sleep-0 { + pins { + pinmux = ; /* TIM8_CH2 */ + }; + }; + + + pwm12_pins_mx: pwm12-0 { + pins { + pinmux = ; /* TIM12_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm12_sleep_pins_mx: pwm12-sleep-0 { + pins { + pinmux = ; /* TIM12_CH2 */ + }; + }; + + sdmmc1_pins_mx: sdmmc1_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins3 { + u-boot,dm-pre-reloc; + pinmux = ; /* SDMMC1_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + uart4_pins_mx: uart4_mx-0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_RX */ + /* pull-up on rx to avoid floating level */ + bias-pull-up; + }; + pins2 { + u-boot,dm-pre-reloc; + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + uart4_sleep_pins_mx: uart4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* UART4_RX */ + ; /* UART4_TX */ + }; + }; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; + + i2c4_pins_z_mx: i2c4_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + + spi6_pins_mx: spi6-0 { + pins1 { + pinmux = , /* SPI6_SCK */ + ; /* SPI6_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI6_MISO */ + bias-disable; + }; + }; + + spi6_sleep_pins_mx: spi6-sleep-0 { + pins { + pinmux = , /* SPI6_SCK */ + , /* SPI6_MISO */ + ; /* SPI6_MOSI */ + }; + }; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + wakeup-source; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + + +&crc1{ + status = "okay"; +}; + +&cryp1{ + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dma1{ + status = "okay"; + sram = <&dma_pool>; +}; + +&dma2{ + status = "okay"; + sram = <&dma_pool>; +}; + +&dts{ + status = "okay"; +}; + +&gpu{ + status = "okay"; + contiguous-area = <&gpu_reserved>; +}; + +&hash1{ + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&hsem{ + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_mx>; + pinctrl-1 = <&i2c1_pins_sleep_mx>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_mx>; + pinctrl-1 = <&i2c2_pins_sleep_mx>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_mx>; + pinctrl-1 = <&i2c5_pins_sleep_mx>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_z_mx>; + pinctrl-1 = <&i2c4_sleep_pins_z_mx>; + status = "okay"; + + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /delete-property/ dmas; + /delete-property/ dma-names; + + pmic:stpmic@33{ + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators{ + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore:buck1{ + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr:buck2{ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd:buck3{ + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3:buck4{ + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio:ldo1{ + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi:ldo2{ + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr:ldo3{ + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb:ldo4{ + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda:ldo5{ + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi:ldo6{ + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr:vref_ddr{ + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out:boost{ + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg:pwr_sw1{ + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw:pwr_sw2{ + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey{ + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ipcc{ + status = "okay"; +}; + +&iwdg2{ + status = "okay"; + timeout-sec = <32>; +}; + +&mdma1{ + status = "okay"; +}; + +&rcc{ + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&rng1{ + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&sdmmc1{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_pins_mx>; + pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; + pinctrl-2 = <&sdmmc1_sleep_pins_mx>; + status = "okay"; + + cd-gpios = <&gpiog 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; +}; + +&tamp{ + status = "okay"; +}; + +&uart4{ + u-boot,dm-pre-reloc; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pins_mx>; + pinctrl-1 = <&uart4_sleep_pins_mx>; + status = "okay"; + + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&usbh_ehci{ + status = "okay"; + phys = <&usbphyc_port0>; +}; + +&usbh_ohci{ + status = "okay"; +}; + +&usbotg_hs{ + u-boot,dm-pre-reloc; + status = "okay"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; +}; + +&usbphyc{ + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbphyc_port0{ + u-boot,dm-pre-reloc; + status = "okay"; + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; +}; + +&usbphyc_port1{ + u-boot,dm-pre-reloc; + status = "okay"; + phy-supply = <&vdd_usb>; + st,phy-tuning = <&usb_phy_tuning>; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0 1>; + status = "okay"; + }; + + adc2: adc@100 { + status = "okay"; + }; + + adc_temp: temp { + status = "okay"; + }; +}; + +&usbh_ohci{ + phys = <&usbphyc_port0>; +}; + +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&sram{ + dma_pool:dma_pool@0{ + reg = <0x50000 0x10000>; + pool; + }; +}; + +&spi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_pins_mx>; + pinctrl-1 = <&spi2_sleep_pins_mx>; + cs-gpios = <&gpioi 0 0>; + status = "okay"; + + spidev2: spidev2@0{ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&spi4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_pins_mx>; + pinctrl-1 = <&spi4_sleep_pins_mx>; + cs-gpios = <&gpioe 11 0>; + status = "okay"; + + spidev4: spidev4@0{ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&spi6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_pins_mx>; + pinctrl-1 = <&spi6_sleep_pins_mx>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; + + spidev6: spidev6@0{ + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_mx>; + pinctrl-1 = <&usart2_sleep_pins_mx>; + pinctrl-2 = <&usart2_idle_pins_mx>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart5_pins_mx>; + pinctrl-1 = <&uart5_sleep_pins_mx>; + pinctrl-2 = <&uart5_idle_pins_mx>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_mx>; + pinctrl-1 = <&uart7_sleep_pins_mx>; + pinctrl-2 = <&uart7_idle_pins_mx>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_mx>; + pinctrl-1 = <&uart8_sleep_pins_mx>; + pinctrl-2 = <&uart8_idle_pins_mx>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default"; + pinctrl-0 = <&m_can1_pins_mx>; + status = "okay"; + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&timers1 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm1: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm1_pins_mx>; + pinctrl-1 = <&pwm1_sleep_pins_mx>; + status = "okay"; + }; +}; + +&timers3 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm3: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm3_pins_mx>; + pinctrl-1 = <&pwm3_sleep_pins_mx>; + status = "okay"; + }; +}; + +&timers4 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm4: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm4_pins_mx>; + pinctrl-1 = <&pwm4_sleep_pins_mx>; + status = "okay"; + }; +}; + +&timers8 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm8: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_mx>; + pinctrl-1 = <&pwm8_sleep_pins_mx>; + status = "okay"; + }; +}; + +&timers12 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm12: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm12_pins_mx>; + pinctrl-1 = <&pwm12_sleep_pins_mx>; + status = "okay"; + }; +}; -- 2.25.1