100 lines
2.0 KiB
Plaintext
100 lines
2.0 KiB
Plaintext
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#mach: crisv10 crisv32
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#sim(crisv10): --hw-device "/rv/trace? true"
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#sim(crisv32): --hw-device "/rv/trace? true"
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#output: /rv: WD\n
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#output: /rv: REG R 0xd0000032\n
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#output: /rv: := 0xabcdef01\n
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#output: /rv: IRQ 0x4\n
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#output: /rv: REG R 0xd0000036\n
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#output: /rv: := 0x76543210\n
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#output: /rv: REG R 0xd0000030\n
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#output: /rv: IRQ 0x0\n
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#output: /rv: IRQ 0x8\n
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#output: /rv: := 0xeeff4455\n
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#output: /rv: REG R 0xd0000034\n
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#output: /rv: := 0xdd001122\n
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#output: /rv: REG R 0xd0000038\n
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#output: /rv: := 0xaaeeff44\n
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#output: /rv: REG R 0xd000003c\n
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#output: /rv: := 0xff445511\n
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#output: pass\n
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# Test two successive ints; that flags are disabled when an interrupt
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# is taken, and then automatically (or by register restore) enabled at
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# return.
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#r W,
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#r r,a8832,abcdef01
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#r I,4
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#r r,a8836,76543210
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#r I,0
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#r I,8
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#r r,a8830,eeff4455
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#r r,a8834,dd001122
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#r r,a8838,aaeeff44
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#r r,a883c,ff445511
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.lcomm dummy,4
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.include "testutils.inc"
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start
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test_h_mem 0xabcdef01 0xd0000032
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moveq -1,$r4
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.if ..asm.arch.cris.v32
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move irqvec1,$ebp
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.else
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move irqvec1,$ibr
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.endif
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ei
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test_h_mem 0,dummy
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; Here after the first interrupt, or perhaps the second interrupt is
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; taken directly; leave it optional. Anyway, the second interrupt
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; should be taken no later than this branch.
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test_h_mem 0,dummy
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killme:
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fail
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irq0x33:
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.if ..asm.arch.cris.v32
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; Nothing needed to save flags - "shift" should happen, and back at rfe.
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.else
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; The missing sim support for interrupt-excluding instructions is matched
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; by the flaw that sim doesn't service interrupts in straight code.
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; So, we can use a sequence that would work on actual hardware.
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move $dccr,$r5
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di
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.endif
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test_h_mem 0x76543210 0xd0000036
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test_h_mem 0xeeff4455 0xd0000030
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test_h_mem 0xdd001122 0xd0000034
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moveq -22,$r4
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.if ..asm.arch.cris.v32
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move irqvec2,$ebp
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rete
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rfe
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.else
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move irqvec2,$ibr
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reti
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move $r5,$dccr
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.endif
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pass
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irq0x34:
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test_h_mem 0xaaeeff44 0xd0000038
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test_h_mem 0xff445511 0xd000003c
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cmpq -22,$r4
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bne killme
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nop
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pass
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singlevec irqvec1,0x33,irq0x33
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singlevec irqvec2,0x34,irq0x34
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