/* This file is part of GDB.
Copyright 2002, 2007 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
--
This file was generated by the program igen */
#ifndef SUPPORT_C
#define SUPPORT_C
#include "sim-main.h"
#include "idecode.h"
#include "itable.h"
#include "support.h"
INLINE_SUPPORT\
(instruction_address)
semantic_illegal
(SIM_DESC sd,
instruction_address cia)
{
#line 93 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
SignalException (ReservedInstruction, 0);
sim_engine_abort (SD, CPU, cia, "Internal function must longjump\n");
return cia;
}
#line 42 "support.c"
INLINE_SUPPORT\
(void)
signal_if_cti
(SIM_DESC sd, instruction_address cia, int MY_INDEX, instruction_word instr)
{
#line 113 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t maj = (instr & 0xfc000000) >> 26;
uint32_t special = instr & 0x3f;
if ((maj & 0x3e) == 0x06 /* Branch/Jump */
|| ((maj & 0x38) == 0 && !((maj & 0x6) == 0))
|| maj == 0x18
|| (maj & 0x37) == 0x32
|| (maj & 0x37) == 0x36
|| ((maj == 0) && (special == 0x9))
/* DERET/ERET/WAIT */
|| ((maj == 0x10) && (instr & 0x02000000)
&& (special == 0x1f || special == 0x18 || special == 0x20)))
{
SignalException (ReservedInstruction, instr);
}
}
#line 65 "support.c"
INLINE_SUPPORT\
(address_word)
delayslot32
(SIM_DESC sd, instruction_address cia, int MY_INDEX, address_word target)
{
#line 135 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
instruction_word delay_insn;
sim_events_slip (SD, 1);
DSPC = CIA;
CIA = CIA + 4; /* NOTE not mips16 */
STATE |= simDELAYSLOT;
delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
signal_if_cti (SD_, delay_insn);
ENGINE_ISSUE_PREFIX_HOOK();
idecode_issue (CPU_, delay_insn, (CIA));
STATE &= ~simDELAYSLOT;
return target;
}
#line 85 "support.c"
INLINE_SUPPORT\
(address_word)
nullify_next_insn32
(SIM_DESC sd, instruction_address cia, int MY_INDEX)
{
#line 171 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
sim_events_slip (SD, 1);
dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
return CIA + 8;
}
#line 97 "support.c"
INLINE_SUPPORT\
(address_word)
loadstore_ea
(SIM_DESC sd, instruction_address cia, int MY_INDEX, address_word base, address_word offset)
{
#line 196 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
return base + offset;
}
#line 107 "support.c"
INLINE_SUPPORT\
(int)
not_word_value
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned_word value)
{
#line 241 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
#if WITH_TARGET_WORD_BITSIZE == 64
return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
#else
return 0;
#endif
}
#line 121 "support.c"
INLINE_SUPPORT\
(void)
unpredictable
(SIM_DESC sd, instruction_address cia, int MY_INDEX)
{
#line 266 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
}
#line 130 "support.c"
INLINE_SUPPORT\
(int)
check_mf_cycles
(SIM_DESC sd, instruction_address cia, int MY_INDEX, hilo_history *history, int64_t time, const char *new)
{
#line 319 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
itable[MY_INDEX].name,
new, (long) CIA,
(long) history->mf.cia);
return 0;
}
return 1;
}
#line 148 "support.c"
INLINE_SUPPORT\
(int)
check_mt_hilo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, hilo_history *history)
{
#line 354 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|| check_mf_cycles (SD_, history, time, "MT"));
history->mt.timestamp = time;
history->mt.cia = CIA;
return ok;
}
#line 163 "support.c"
INLINE_SUPPORT\
(int)
check_mf_hilo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, hilo_history *history, hilo_history *peer)
{
#line 403 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t time = sim_events_time (SD);
int ok = 1;
if (peer != NULL
&& peer->mt.timestamp > history->op.timestamp
&& history->mt.timestamp < history->op.timestamp
&& ! (history->mf.timestamp > history->op.timestamp
&& history->mf.timestamp < peer->mt.timestamp)
&& ! (peer->mf.timestamp > history->op.timestamp
&& peer->mf.timestamp < peer->mt.timestamp))
{
/* The peer has been written to since the last OP yet we have
not */
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
itable[MY_INDEX].name,
(long) CIA,
(long) history->op.cia,
(long) peer->mt.cia);
ok = 0;
}
history->mf.timestamp = time;
history->mf.cia = CIA;
return ok;
}
#line 194 "support.c"
INLINE_SUPPORT\
(int)
check_mult_hilo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, hilo_history *hi, hilo_history *lo)
{
#line 455 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
#line 212 "support.c"
INLINE_SUPPORT\
(int)
check_div_hilo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, hilo_history *hi, hilo_history *lo)
{
#line 514 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
#line 230 "support.c"
INLINE_SUPPORT\
(void)
check_u64
(SIM_DESC sd, instruction_address cia, int MY_INDEX, instruction_word insn)
{
#line 560 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
#line 240 "support.c"
INLINE_SUPPORT\
(void)
do_add
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 591 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU32_BEGIN (GPR[rs]);
ALU32_ADD (GPR[rt]);
ALU32_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
#line 258 "support.c"
INLINE_SUPPORT\
(void)
do_addi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 604 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
{
ALU32_BEGIN (GPR[rs]);
ALU32_ADD (EXTEND16 (immediate));
ALU32_END (GPR[rt]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rt]);
}
#line 276 "support.c"
INLINE_SUPPORT\
(void)
do_andi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, unsigned int immediate)
{
#line 617 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = GPR[rs] & immediate;
TRACE_ALU_RESULT (GPR[rt]);
}
#line 288 "support.c"
INLINE_SUPPORT\
(void)
do_dadd
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 624 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU64_BEGIN (GPR[rs]);
ALU64_ADD (GPR[rt]);
ALU64_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
#line 304 "support.c"
INLINE_SUPPORT\
(void)
do_daddi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int immediate)
{
#line 635 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
{
ALU64_BEGIN (GPR[rs]);
ALU64_ADD (EXTEND16 (immediate));
ALU64_END (GPR[rt]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rt]);
}
#line 320 "support.c"
INLINE_SUPPORT\
(void)
do_dsll32
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 646 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = GPR[rt] << s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 333 "support.c"
INLINE_SUPPORT\
(void)
do_dsra32
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 654 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 346 "support.c"
INLINE_SUPPORT\
(void)
do_dsrl32
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 662 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 359 "support.c"
INLINE_SUPPORT\
(void)
do_dsub
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 670 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU64_BEGIN (GPR[rs]);
ALU64_SUB (GPR[rt]);
ALU64_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
#line 375 "support.c"
INLINE_SUPPORT\
(void)
do_break
(SIM_DESC sd, instruction_address cia, int MY_INDEX, address_word instruction_0)
{
#line 681 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
/* Check for some break instruction which are reserved for use by the
simulator. */
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
sim_engine_halt (SD, CPU, NULL, cia,
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
if (STATE & simDELAYSLOT)
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
}
else
{
/* If we get this far, we're not an instruction reserved by the sim. Raise
the exception. */
SignalException (BreakPoint, instruction_0);
}
}
#line 409 "support.c"
INLINE_SUPPORT\
(void)
do_break16
(SIM_DESC sd, instruction_address cia, int MY_INDEX, address_word instruction_0)
{
#line 710 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (STATE & simDELAYSLOT)
PC = cia - 2; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
}
#line 423 "support.c"
INLINE_SUPPORT\
(void)
do_clo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs)
{
#line 719 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t temp = GPR[rs];
uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 445 "support.c"
INLINE_SUPPORT\
(void)
do_clz
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs)
{
#line 736 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t temp = GPR[rs];
uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 467 "support.c"
INLINE_SUPPORT\
(void)
do_dclo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs)
{
#line 753 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp = GPR[rs];
uint32_t i;
uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 488 "support.c"
INLINE_SUPPORT\
(void)
do_dclz
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs)
{
#line 769 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp = GPR[rs];
uint32_t i;
uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 509 "support.c"
INLINE_SUPPORT\
(void)
do_lb
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 785 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
EXTEND16 (offset)));
}
#line 520 "support.c"
INLINE_SUPPORT\
(void)
do_lh
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 791 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
EXTEND16 (offset)));
}
#line 531 "support.c"
INLINE_SUPPORT\
(void)
do_lwr
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 797 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset), GPR[rt]));
}
#line 542 "support.c"
INLINE_SUPPORT\
(void)
do_lwl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 803 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset), GPR[rt]));
}
#line 553 "support.c"
INLINE_SUPPORT\
(void)
do_lwc
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int num, int rt, int offset, int base)
{
#line 809 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset)));
}
#line 564 "support.c"
INLINE_SUPPORT\
(void)
do_lw
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 815 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset)));
}
#line 575 "support.c"
INLINE_SUPPORT\
(void)
do_lwu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base, address_word instruction_0)
{
#line 821 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_u64 (SD_, instruction_0);
GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
}
#line 586 "support.c"
INLINE_SUPPORT\
(void)
do_lhu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 827 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
}
#line 596 "support.c"
INLINE_SUPPORT\
(void)
do_ldc
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int num, int rt, int offset, int base)
{
#line 832 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
EXTEND16 (offset)));
}
#line 607 "support.c"
INLINE_SUPPORT\
(void)
do_lbu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 838 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
}
#line 617 "support.c"
INLINE_SUPPORT\
(void)
do_ll
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int insn_offset, int basereg)
{
#line 843 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[basereg];
address_word offset = EXTEND16 (insn_offset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
sim_core_unaligned_signal);
}
else
{
uint64_t memval = 0;
uint64_t memval1 = 0;
uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
isDATA, isREAL);
byte = ((vaddr & mask) ^ (bigend << shift));
GPR[rt] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1;
}
}
}
#line 653 "support.c"
INLINE_SUPPORT\
(void)
do_lld
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int roffset, int rbase)
{
#line 874 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 7) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
sim_core_unaligned_signal);
}
else
{
uint64_t memval = 0;
uint64_t memval1 = 0;
LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
isDATA, isREAL);
GPR[rt] = memval;
LLBIT = 1;
}
}
}
#line 683 "support.c"
INLINE_SUPPORT\
(void)
do_lui
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int immediate)
{
#line 899 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT1 (immediate);
GPR[rt] = EXTEND32 (immediate << 16);
TRACE_ALU_RESULT (GPR[rt]);
}
#line 695 "support.c"
INLINE_SUPPORT\
(void)
do_madd
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 906 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
#line 714 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_madd
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 920 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
#line 735 "support.c"
INLINE_SUPPORT\
(void)
do_maddu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 936 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
#line 755 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_maddu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 951 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
if (ac == 0)
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
#line 778 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_mfhi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rd)
{
#line 969 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (ac == 0)
do_mfhi (SD_, rd);
else
GPR[rd] = DSPHI(ac);
}
#line 791 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_mflo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rd)
{
#line 977 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (ac == 0)
do_mflo (SD_, rd);
else
GPR[rd] = DSPLO(ac);
}
#line 804 "support.c"
INLINE_SUPPORT\
(void)
do_movn
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 985 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (GPR[rt] != 0)
{
GPR[rd] = GPR[rs];
TRACE_ALU_RESULT (GPR[rd]);
}
}
#line 818 "support.c"
INLINE_SUPPORT\
(void)
do_movz
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 994 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (GPR[rt] == 0)
{
GPR[rd] = GPR[rs];
TRACE_ALU_RESULT (GPR[rd]);
}
}
#line 832 "support.c"
INLINE_SUPPORT\
(void)
do_msub
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 1003 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
#line 851 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_msub
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 1017 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
#line 872 "support.c"
INLINE_SUPPORT\
(void)
do_msubu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 1033 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
#line 891 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_msubu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 1047 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
#line 912 "support.c"
INLINE_SUPPORT\
(void)
do_mthi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs)
{
#line 1063 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_mt_hilo (SD_, HIHISTORY);
HI = GPR[rs];
}
#line 923 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_mthi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs)
{
#line 1069 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (ac == 0)
check_mt_hilo (SD_, HIHISTORY);
DSPHI(ac) = GPR[rs];
}
#line 935 "support.c"
INLINE_SUPPORT\
(void)
do_mtlo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs)
{
#line 1076 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_mt_hilo (SD_, LOHISTORY);
LO = GPR[rs];
}
#line 946 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_mtlo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs)
{
#line 1082 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (ac == 0)
check_mt_hilo (SD_, LOHISTORY);
DSPLO(ac) = GPR[rs];
}
#line 958 "support.c"
INLINE_SUPPORT\
(void)
do_mul
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 1089 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t prod;
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((int64_t)(int32_t) GPR[rs])
* ((int64_t)(int32_t) GPR[rt]));
GPR[rd] = EXTEND32 (VL4_8 (prod));
TRACE_ALU_RESULT (GPR[rd]);
}
#line 975 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_mult
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 1101 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = ((int64_t)(int32_t) GPR[rs])
* ((int64_t)(int32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
{
ACX = 0; /* SmartMIPS */
TRACE_ALU_RESULT2 (HI, LO);
}
}
#line 999 "support.c"
INLINE_SUPPORT\
(void)
do_dsp_multu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 1120 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = ((uint64_t)(uint32_t) GPR[rs])
* ((uint64_t)(uint32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
#line 1020 "support.c"
INLINE_SUPPORT\
(void)
do_pref
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int hint, int insn_offset, int insn_base)
{
#line 1136 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[insn_base];
address_word offset = EXTEND16 (insn_offset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
/* Prefetch (paddr, vaddr, isDATA, hint); */
}
}
#line 1036 "support.c"
INLINE_SUPPORT\
(void)
do_sc
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit)
{
#line 1147 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t instruction = instruction_0;
address_word base = GPR[basereg];
address_word offset = EXTEND16 (offsetarg);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
sim_core_unaligned_signal);
}
else
{
uint64_t memval = 0;
uint64_t memval1 = 0;
uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = ((uint64_t) GPR[rt] << (8 * byte));
if (LLBIT)
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
if (store_ll_bit)
GPR[rt] = LLBIT;
}
}
}
#line 1077 "support.c"
INLINE_SUPPORT\
(void)
do_scd
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int roffset, int rbase, int store_ll_bit)
{
#line 1183 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 7) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
sim_core_unaligned_signal);
}
else
{
uint64_t memval = 0;
uint64_t memval1 = 0;
memval = GPR[rt];
if (LLBIT)
StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
isREAL);
if (store_ll_bit)
GPR[rt] = LLBIT;
}
}
}
#line 1109 "support.c"
INLINE_SUPPORT\
(void)
do_sub
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 1210 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU32_BEGIN (GPR[rs]);
ALU32_SUB (GPR[rt]);
ALU32_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
#line 1127 "support.c"
INLINE_SUPPORT\
(void)
do_sw
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int offset, int base)
{
#line 1223 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]);
}
#line 1137 "support.c"
INLINE_SUPPORT\
(void)
do_teq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, address_word instruction_0)
{
#line 1228 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] == (signed_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1148 "support.c"
INLINE_SUPPORT\
(void)
do_teqi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1234 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1159 "support.c"
INLINE_SUPPORT\
(void)
do_tge
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, address_word instruction_0)
{
#line 1240 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] >= (signed_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1170 "support.c"
INLINE_SUPPORT\
(void)
do_tgei
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1246 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1181 "support.c"
INLINE_SUPPORT\
(void)
do_tgeiu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1252 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1192 "support.c"
INLINE_SUPPORT\
(void)
do_tgeu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs ,int rt, address_word instruction_0)
{
#line 1258 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1203 "support.c"
INLINE_SUPPORT\
(void)
do_tlt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, address_word instruction_0)
{
#line 1264 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] < (signed_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1214 "support.c"
INLINE_SUPPORT\
(void)
do_tlti
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1270 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1225 "support.c"
INLINE_SUPPORT\
(void)
do_tltiu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1276 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1236 "support.c"
INLINE_SUPPORT\
(void)
do_tltu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, address_word instruction_0)
{
#line 1282 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1247 "support.c"
INLINE_SUPPORT\
(void)
do_tne
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, address_word instruction_0)
{
#line 1288 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] != (signed_word) GPR[rt])
SignalException (Trap, instruction_0);
}
#line 1258 "support.c"
INLINE_SUPPORT\
(void)
do_tnei
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int immediate, address_word instruction_0)
{
#line 1294 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate))
SignalException (Trap, instruction_0);
}
#line 1269 "support.c"
INLINE_SUPPORT\
(void)
do_abs_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1300 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt));
}
#line 1281 "support.c"
INLINE_SUPPORT\
(void)
do_add_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int ft, address_word instruction_0)
{
#line 1307 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
}
#line 1293 "support.c"
INLINE_SUPPORT\
(void)
do_alnv_ps
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, int rs, address_word instruction_0)
{
#line 1314 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t fsx;
uint64_t ftx;
uint64_t fdx;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
fsx = ValueFPR (fs, fmt_ps);
if ((GPR[rs] & 0x3) != 0)
Unpredictable ();
if ((GPR[rs] & 0x4) == 0)
fdx = fsx;
else
{
ftx = ValueFPR (ft, fmt_ps);
if (BigEndianCPU)
fdx = PackPS (PSLower (fsx), PSUpper (ftx));
else
fdx = PackPS (PSLower (ftx), PSUpper (fsx));
}
StoreFPR (fd, fmt_ps, fdx);
}
#line 1321 "support.c"
INLINE_SUPPORT\
(void)
do_c_cond_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int cond, int fmt, int cc, int fs, int ft, address_word instruction_0)
{
#line 1337 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc);
TRACE_ALU_RESULT (ValueFCR (31));
}
#line 1334 "support.c"
INLINE_SUPPORT\
(void)
do_ceil_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int type, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1345 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt,
type));
}
#line 1347 "support.c"
INLINE_SUPPORT\
(void)
do_cfc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1353 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31)
{
unsigned_word fcr = ValueFCR (fs);
TRACE_ALU_INPUT1 (fcr);
GPR[rt] = fcr;
}
/* else NOP */
TRACE_ALU_RESULT (GPR[rt]);
}
#line 1365 "support.c"
INLINE_SUPPORT\
(void)
do_ctc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1366 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
TRACE_ALU_INPUT1 (GPR[rt]);
if (fs == 25 || fs == 26 || fs == 28 || fs == 31)
StoreFCR (fs, GPR[rt]);
/* else NOP */
}
#line 1379 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_d_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1375 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if ((fmt == fmt_double) | 0)
SignalException (ReservedInstruction, instruction_0);
StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
fmt_double));
}
#line 1393 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_l_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1384 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
SignalException (ReservedInstruction, instruction_0);
StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
fmt_long));
}
#line 1407 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_ps_s
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, address_word instruction_0)
{
#line 1393 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single),
ValueFPR (ft, fmt_single)));
}
#line 1420 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_s_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1401 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if ((fmt == fmt_single) | 0)
SignalException (ReservedInstruction, instruction_0);
StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
fmt_single));
}
#line 1434 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_s_pl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, address_word instruction_0)
{
#line 1410 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps)));
}
#line 1446 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_s_pu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, address_word instruction_0)
{
#line 1417 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps)));
}
#line 1458 "support.c"
INLINE_SUPPORT\
(void)
do_cvt_w_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1424 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
SignalException (ReservedInstruction, instruction_0);
StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
fmt_word));
}
#line 1472 "support.c"
INLINE_SUPPORT\
(void)
do_div_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int ft, address_word instruction_0)
{
#line 1433 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
}
#line 1483 "support.c"
INLINE_SUPPORT\
(void)
do_dmfc1b
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1448 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (SizeFGR () == 64)
GPR[rt] = FGR[fs];
else if ((fs & 0x1) == 0)
GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
else
Unpredictable ();
TRACE_ALU_RESULT (GPR[rt]);
}
#line 1499 "support.c"
INLINE_SUPPORT\
(void)
do_dmtc1b
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1459 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (SizeFGR () == 64)
StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
else if ((fs & 0x1) == 0)
StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
else
Unpredictable ();
}
#line 1514 "support.c"
INLINE_SUPPORT\
(void)
do_floor_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int type, int fmt, int fd, int fs)
{
#line 1469 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt,
type));
}
#line 1526 "support.c"
INLINE_SUPPORT\
(void)
do_luxc1_64
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int rindex, int rbase)
{
#line 1492 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word index = GPR[rindex];
address_word vaddr = base + index;
if (SizeFGR () != 64)
Unpredictable ();
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
if ((vaddr & 0x7) != 0)
index -= (vaddr & 0x7);
COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
}
#line 1545 "support.c"
INLINE_SUPPORT\
(void)
do_lwc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ft, int offset, int base)
{
#line 1506 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset)));
}
#line 1557 "support.c"
INLINE_SUPPORT\
(void)
do_lwxc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int index, int base, address_word instruction_0)
{
#line 1513 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
}
#line 1569 "support.c"
INLINE_SUPPORT\
(void)
do_madd_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fr, int fs, int ft, address_word instruction_0)
{
#line 1520 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
ValueFPR (fr, fmt), fmt));
}
#line 1583 "support.c"
INLINE_SUPPORT\
(void)
do_mfc1b
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1529 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
GPR[rt] = EXTEND32 (FGR[fs]);
TRACE_ALU_RESULT (GPR[rt]);
}
#line 1595 "support.c"
INLINE_SUPPORT\
(void)
do_mov_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1536 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, ValueFPR (fs, fmt));
}
#line 1607 "support.c"
INLINE_SUPPORT\
(void)
do_movtf
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int tf, int rd, int rs, int cc)
{
#line 1543 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if (GETFCC(cc) == tf)
GPR[rd] = GPR[rs];
}
#line 1619 "support.c"
INLINE_SUPPORT\
(void)
do_movtf_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int tf, int fmt, int fd, int fs, int cc)
{
#line 1550 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if (fmt != fmt_ps)
{
if (GETFCC(cc) == tf)
StoreFPR (fd, fmt, ValueFPR (fs, fmt));
else
StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */
}
else
{
uint64_t fdx;
fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
fmt_ps)),
PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
fmt_ps)));
StoreFPR (fd, fmt_ps, fdx);
}
}
#line 1645 "support.c"
INLINE_SUPPORT\
(void)
do_movn_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int rt)
{
#line 1571 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if (GPR[rt] != 0)
StoreFPR (fd, fmt, ValueFPR (fs, fmt));
else
StoreFPR (fd, fmt, ValueFPR (fd, fmt));
}
#line 1659 "support.c"
INLINE_SUPPORT\
(void)
do_movz_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int rt)
{
#line 1580 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
if (GPR[rt] == 0)
StoreFPR (fd, fmt, ValueFPR (fs, fmt));
else
StoreFPR (fd, fmt, ValueFPR (fd, fmt));
}
#line 1673 "support.c"
INLINE_SUPPORT\
(void)
do_msub_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fr, int fs, int ft, address_word instruction_0)
{
#line 1589 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
ValueFPR (fr, fmt), fmt));
}
#line 1687 "support.c"
INLINE_SUPPORT\
(void)
do_mtc1b
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 1598 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
}
#line 1698 "support.c"
INLINE_SUPPORT\
(void)
do_mul_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int ft, address_word instruction_0)
{
#line 1604 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
}
#line 1710 "support.c"
INLINE_SUPPORT\
(void)
do_neg_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, address_word instruction_0)
{
#line 1611 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt));
}
#line 1722 "support.c"
INLINE_SUPPORT\
(void)
do_nmadd_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fr, int fs, int ft, address_word instruction_0)
{
#line 1618 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
ValueFPR (fr, fmt), fmt));
}
#line 1736 "support.c"
INLINE_SUPPORT\
(void)
do_nmsub_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fr, int fs, int ft, address_word instruction_0)
{
#line 1627 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
ValueFPR (fr, fmt), fmt));
}
#line 1750 "support.c"
INLINE_SUPPORT\
(void)
do_pll_ps
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, address_word instruction_0)
{
#line 1636 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
PSLower (ValueFPR (ft, fmt_ps))));
}
#line 1763 "support.c"
INLINE_SUPPORT\
(void)
do_plu_ps
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, address_word instruction_0)
{
#line 1644 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
PSUpper (ValueFPR (ft, fmt_ps))));
}
#line 1776 "support.c"
INLINE_SUPPORT\
(void)
do_pul_ps
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, address_word instruction_0)
{
#line 1652 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
PSLower (ValueFPR (ft, fmt_ps))));
}
#line 1789 "support.c"
INLINE_SUPPORT\
(void)
do_puu_ps
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fd, int fs, int ft, address_word instruction_0)
{
#line 1660 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
PSUpper (ValueFPR (ft, fmt_ps))));
}
#line 1802 "support.c"
INLINE_SUPPORT\
(void)
do_recip_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs)
{
#line 1668 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt));
}
#line 1813 "support.c"
INLINE_SUPPORT\
(void)
do_round_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int type, int fmt, int fd, int fs)
{
#line 1674 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt,
type));
}
#line 1825 "support.c"
INLINE_SUPPORT\
(void)
do_rsqrt_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs)
{
#line 1681 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt));
}
#line 1836 "support.c"
INLINE_SUPPORT\
(void)
do_prefx
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int hint, int rindex, int rbase)
{
#line 1687 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word index = GPR[rindex];
{
address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr = vaddr;
/* Prefetch (paddr, vaddr, isDATA, hint); */
}
}
#line 1852 "support.c"
INLINE_SUPPORT\
(void)
do_suxc1_64
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fs, int rindex, int rbase)
{
#line 1725 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word index = GPR[rindex];
address_word vaddr = base + index;
if (SizeFGR () != 64)
Unpredictable ();
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
if ((vaddr & 0x7) != 0)
index -= (vaddr & 0x7);
do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs));
}
#line 1870 "support.c"
INLINE_SUPPORT\
(void)
do_sqrt_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs)
{
#line 1738 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt)));
}
#line 1881 "support.c"
INLINE_SUPPORT\
(void)
do_sub_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, int fd, int fs, int ft, address_word instruction_0)
{
#line 1744 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
}
#line 1893 "support.c"
INLINE_SUPPORT\
(void)
do_swc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ft, int roffset, int rbase, address_word instruction_0)
{
#line 1751 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
check_fpu (SD_);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
write_transfer, sim_core_unaligned_signal);
}
else
{
uword64 memval = 0;
uword64 memval1 = 0;
uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
}
}
}
#line 1930 "support.c"
INLINE_SUPPORT\
(void)
do_swxc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fs, int rindex, int rbase, address_word instruction_0)
{
#line 1783 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word index = GPR[rindex];
check_fpu (SD_);
check_u64 (SD_, instruction_0);
{
address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr = vaddr;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
sim_core_unaligned_signal);
}
else
{
uint64_t memval = 0;
uint64_t memval1 = 0;
uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte));
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
}
}
}
#line 1969 "support.c"
INLINE_SUPPORT\
(void)
do_trunc_fmt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int type, int fmt, int fd, int fs)
{
#line 1817 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_fpu (SD_);
StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt,
type));
}
#line 1981 "support.c"
INLINE_SUPPORT\
(void)
do_addiu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 1866 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
TRACE_ALU_RESULT (GPR[rt]);
}
#line 1995 "support.c"
INLINE_SUPPORT\
(void)
do_addu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 1897 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2009 "support.c"
INLINE_SUPPORT\
(void)
do_and
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 1928 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] & GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2021 "support.c"
INLINE_SUPPORT\
(void)
do_daddiu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 2519 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
TRACE_ALU_RESULT (GPR[rt]);
}
#line 2033 "support.c"
INLINE_SUPPORT\
(void)
do_daddu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 2543 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] + GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2045 "support.c"
INLINE_SUPPORT\
(void)
do_ddiv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 2599 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
int64_t n = GPR[rs];
int64_t d = GPR[rt];
int64_t hi;
int64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else
{
lo = (n / d);
hi = (n % d);
}
HI = hi;
LO = lo;
}
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2080 "support.c"
INLINE_SUPPORT\
(void)
do_ddivu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 2645 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
uint64_t n = GPR[rs];
uint64_t d = GPR[rt];
uint64_t hi;
uint64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
hi = 0;
}
else
{
lo = (n / d);
hi = (n % d);
}
HI = hi;
LO = lo;
}
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2110 "support.c"
INLINE_SUPPORT\
(void)
do_div
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 2684 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
int32_t n = GPR[rs];
int32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else if (n == SIGNED32 (0x80000000) && d == -1)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else
{
LO = EXTEND32 (n / d);
HI = EXTEND32 (n % d);
}
}
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2141 "support.c"
INLINE_SUPPORT\
(void)
do_divu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt)
{
#line 2730 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
uint32_t n = GPR[rs];
uint32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
else
{
LO = EXTEND32 (n / d);
HI = EXTEND32 (n % d);
}
}
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2167 "support.c"
INLINE_SUPPORT\
(void)
do_dmultx
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd, int signed_p)
{
#line 2770 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t lo;
uint64_t hi;
uint64_t m00;
uint64_t m01;
uint64_t m10;
uint64_t m11;
uint64_t mid;
int sign;
uint64_t op1 = GPR[rs];
uint64_t op2 = GPR[rt];
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
/* make signed multiply unsigned */
sign = 0;
if (signed_p)
{
if ((int64_t) op1 < 0)
{
op1 = - op1;
++sign;
}
if ((int64_t) op2 < 0)
{
op2 = - op2;
++sign;
}
}
/* multiply out the 4 sub products */
m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2));
m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2));
m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2));
m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2));
/* add the products */
mid = ((uint64_t) VH4_8 (m00)
+ (uint64_t) VL4_8 (m10)
+ (uint64_t) VL4_8 (m01));
lo = U8_4 (mid, m00);
hi = (m11
+ (uint64_t) VH4_8 (mid)
+ (uint64_t) VH4_8 (m01)
+ (uint64_t) VH4_8 (m10));
/* fix the sign */
if (sign & 1)
{
lo = -lo;
if (lo == 0)
hi = -hi;
else
hi = -hi - 1;
}
/* save the result HI/LO (and a gpr) */
LO = lo;
HI = hi;
if (rd != 0)
GPR[rd] = lo;
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2232 "support.c"
INLINE_SUPPORT\
(void)
do_dmult
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 2830 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
do_dmultx (SD_, rs, rt, rd, 1);
}
#line 2242 "support.c"
INLINE_SUPPORT\
(void)
do_dmultu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 2859 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
do_dmultx (SD_, rs, rt, rd, 0);
}
#line 2252 "support.c"
INLINE_SUPPORT\
(uint64_t)
do_dror
(SIM_DESC sd, instruction_address cia, int MY_INDEX, uint64_t x,uint64_t y)
{
#line 2887 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t result;
y &= 63;
TRACE_ALU_INPUT2 (x, y);
result = ROTR64 (x, y);
TRACE_ALU_RESULT (result);
return result;
}
#line 2268 "support.c"
INLINE_SUPPORT\
(void)
do_dsll
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 2932 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = GPR[rt] << shift;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2280 "support.c"
INLINE_SUPPORT\
(void)
do_dsllv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 2970 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = GPR[rt] << s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2293 "support.c"
INLINE_SUPPORT\
(void)
do_dsra
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 2993 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = ((int64_t) GPR[rt]) >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2305 "support.c"
INLINE_SUPPORT\
(void)
do_dsrav
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 3033 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2318 "support.c"
INLINE_SUPPORT\
(void)
do_dsrl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 3056 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = (uint64_t) GPR[rt] >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2330 "support.c"
INLINE_SUPPORT\
(void)
do_dsrlv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 3096 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2343 "support.c"
INLINE_SUPPORT\
(void)
do_dsubu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 3138 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] - GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2355 "support.c"
INLINE_SUPPORT\
(unsigned_word)
do_load
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset)
{
#line 3275 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
}
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte));
}
#line 2381 "support.c"
INLINE_SUPPORT\
(unsigned_word)
do_load_left
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset, unsigned_word rt)
{
#line 3296 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
unsigned int word;
address_word paddr;
uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
unsigned_word lhs_mask;
unsigned_word temp;
paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
/* compute where within the word/mem we are */
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
nr_lhs_bits = 8 * byte + 8;
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
(long) ((uint64_t) vaddr >> 32), (long) vaddr,
(long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
if (word == 0)
{
/* GPR_31..32-NR_LHS_BITS_ = memval_NR_LHS_BITS-1..0_ */
temp = (memval << nr_rhs_bits);
}
else
{
/* GPR_31..32-NR_LHS_BITS = memval_32+NR_LHS_BITS..32_ */
temp = (memval >> nr_lhs_bits);
}
lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((uint64_t) memval >> 32), (long) memval,
(long) ((uint64_t) temp >> 32), (long) temp,
(long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask,
(long) (rt >> 32), (long) rt); */
return rt;
}
#line 2440 "support.c"
INLINE_SUPPORT\
(unsigned_word)
do_load_right
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset, unsigned_word rt)
{
#line 3350 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr = paddr & ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
(long) paddr, byte, (long) paddr, (long) memval); */
{
unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
rt &= ~screen;
rt |= (memval >> (8 * byte)) & screen;
}
return rt;
}
#line 2473 "support.c"
INLINE_SUPPORT\
(void)
do_mfhi
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd)
{
#line 3718 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT1 (HI);
GPR[rd] = HI;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2486 "support.c"
INLINE_SUPPORT\
(void)
do_mflo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd)
{
#line 3754 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
TRACE_ALU_INPUT1 (LO);
GPR[rd] = LO;
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2499 "support.c"
INLINE_SUPPORT\
(void)
do_mult
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 3931 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((int64_t)(int32_t) GPR[rs])
* ((int64_t)(int32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
ACX = 0; /* SmartMIPS */
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2521 "support.c"
INLINE_SUPPORT\
(void)
do_multu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 3984 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((uint64_t)(uint32_t) GPR[rs])
* ((uint64_t)(uint32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
#line 2542 "support.c"
INLINE_SUPPORT\
(void)
do_nor
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4036 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = ~ (GPR[rs] | GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2554 "support.c"
INLINE_SUPPORT\
(void)
do_or
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4064 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = (GPR[rs] | GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2566 "support.c"
INLINE_SUPPORT\
(void)
do_ori
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, unsigned immediate)
{
#line 4093 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = (GPR[rs] | immediate);
TRACE_ALU_RESULT (GPR[rt]);
}
#line 2578 "support.c"
INLINE_SUPPORT\
(uint64_t)
do_ror
(SIM_DESC sd, instruction_address cia, int MY_INDEX, uint32_t x,uint32_t y)
{
#line 4135 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint64_t result;
y &= 31;
TRACE_ALU_INPUT2 (x, y);
result = EXTEND32 (ROTR32 (x, y));
TRACE_ALU_RESULT (result);
return result;
}
#line 2594 "support.c"
INLINE_SUPPORT\
(void)
do_store
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset, unsigned_word word)
{
#line 4173 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
}
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = (word << (8 * byte));
StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
}
#line 2620 "support.c"
INLINE_SUPPORT\
(void)
do_store_left
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset, unsigned_word rt)
{
#line 4194 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
unsigned int word;
address_word paddr;
uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
/* compute where within the word/mem we are */
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
nr_lhs_bits = 8 * byte + 8;
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
(long) ((uint64_t) vaddr >> 32), (long) vaddr,
(long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
if (word == 0)
{
memval = (rt >> nr_rhs_bits);
}
else
{
memval = (rt << nr_lhs_bits);
}
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((uint64_t) rt >> 32), (long) rt,
(long) ((uint64_t) memval >> 32), (long) memval); */
StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
}
#line 2668 "support.c"
INLINE_SUPPORT\
(void)
do_store_right
(SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned access, address_word base, address_word offset, unsigned_word rt)
{
#line 4237 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = (ReverseEndian ? -1 : 0);
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr &= ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
memval = (rt << (byte * 8));
StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
}
#line 2692 "support.c"
INLINE_SUPPORT\
(void)
do_sll
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 4395 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t temp = (GPR[rt] << shift);
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2705 "support.c"
INLINE_SUPPORT\
(void)
do_sllv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4437 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED (GPR[rs], 4, 0);
uint32_t temp = (GPR[rt] << s);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2719 "support.c"
INLINE_SUPPORT\
(void)
do_slt
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4467 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2731 "support.c"
INLINE_SUPPORT\
(void)
do_slti
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 4495 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
TRACE_ALU_RESULT (GPR[rt]);
}
#line 2743 "support.c"
INLINE_SUPPORT\
(void)
do_sltiu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 4523 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
TRACE_ALU_RESULT (GPR[rt]);
}
#line 2755 "support.c"
INLINE_SUPPORT\
(void)
do_sltu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4552 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2767 "support.c"
INLINE_SUPPORT\
(void)
do_sra
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 4580 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int32_t temp = (int32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2782 "support.c"
INLINE_SUPPORT\
(void)
do_srav
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4612 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED (GPR[rs], 4, 0);
int32_t temp = (int32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2798 "support.c"
INLINE_SUPPORT\
(void)
do_srl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd, int shift)
{
#line 4645 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
uint32_t temp = (uint32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2813 "support.c"
INLINE_SUPPORT\
(void)
do_srlv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4676 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
int s = MASKED (GPR[rs], 4, 0);
uint32_t temp = (uint32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2829 "support.c"
INLINE_SUPPORT\
(void)
do_subu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 4729 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2843 "support.c"
INLINE_SUPPORT\
(void)
do_xor
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int rd)
{
#line 5095 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = GPR[rs] ^ GPR[rt];
TRACE_ALU_RESULT (GPR[rd]);
}
#line 2855 "support.c"
INLINE_SUPPORT\
(void)
do_xori
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, uint16_t immediate)
{
#line 5123 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = GPR[rs] ^ immediate;
TRACE_ALU_RESULT (GPR[rt]);
}
#line 2867 "support.c"
INLINE_SUPPORT\
(const char *)
str_FMT
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt)
{
#line 5158 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
switch (fmt)
{
case fmt_single: return "s";
case fmt_double: return "d";
case fmt_word: return "w";
case fmt_long: return "l";
case fmt_ps: return "ps";
default: return "?";
}
}
#line 2885 "support.c"
INLINE_SUPPORT\
(const char *)
str_TF
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int tf)
{
#line 5171 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (tf)
return "t";
else
return "f";
}
#line 2898 "support.c"
INLINE_SUPPORT\
(const char *)
str_ND
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int nd)
{
#line 5179 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (nd)
return "l";
else
return "";
}
#line 2911 "support.c"
INLINE_SUPPORT\
(const char *)
str_COND
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int cond)
{
#line 5187 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
switch (cond)
{
case 00: return "f";
case 01: return "un";
case 02: return "eq";
case 03: return "ueq";
case 04: return "olt";
case 05: return "ult";
case 06: return "ole";
case 07: return "ule";
case 010: return "sf";
case 011: return "ngle";
case 012: return "seq";
case 013: return "ngl";
case 014: return "lt";
case 015: return "nge";
case 016: return "le";
case 017: return "ngt";
default: return "?";
}
}
#line 2940 "support.c"
INLINE_SUPPORT\
(void)
check_fmt_p
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int fmt, instruction_word insn)
{
#line 5229 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
/* None of these ISAs support Paired Single, so just fall back to
the single/double check. */
if ((fmt != fmt_single) && (fmt != fmt_double))
SignalException (ReservedInstruction, insn);
}
#line 2953 "support.c"
INLINE_SUPPORT\
(void)
check_fpu
(SIM_DESC sd, instruction_address cia, int MY_INDEX)
{
#line 5277 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
if (! COP_Usable (1))
SignalExceptionCoProcessorUnusable (1);
FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask);
sim_fpu_quiet_nan_inverted = true;
}
#line 2967 "support.c"
INLINE_SUPPORT\
(void)
do_cache
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int op, int rbase, int roffset, address_word instruction_0)
{
#line 6626 "/home/ubuntu/data/data/method/gdb/gdb-13.2/sim/mips/mips.igen"
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
CacheOp(op, vaddr, paddr, instruction_0);
}
}
#line 2983 "support.c"
INLINE_SUPPORT\
(void)
do_dsbh
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 24 "mips3264r2.igen"
union { uint64_t d; uint16_t h[4]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.d = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
u.h[2] = SWAP_2 (u.h[2]);
u.h[3] = SWAP_2 (u.h[3]);
GPR[rd] = u.d;
TRACE_ALU_RESULT1 (GPR[rd]);
}
#line 3001 "support.c"
INLINE_SUPPORT\
(void)
do_dshd
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 37 "mips3264r2.igen"
uint64_t d;
TRACE_ALU_INPUT1 (GPR[rt]);
d = GPR[rt];
GPR[rd] = ((d >> 48)
| (d << 48)
| ((d & 0x0000ffff00000000ULL) >> 16)
| ((d & 0x00000000ffff0000ULL) << 16));
TRACE_ALU_RESULT1 (GPR[rd]);
}
#line 3018 "support.c"
INLINE_SUPPORT\
(void)
do_dext
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int size)
{
#line 49 "mips3264r2.igen"
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3030 "support.c"
INLINE_SUPPORT\
(void)
do_dextm
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int size)
{
#line 56 "mips3264r2.igen"
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size + 32, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3042 "support.c"
INLINE_SUPPORT\
(void)
do_dextu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int size)
{
#line 63 "mips3264r2.igen"
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + 32 + size, lsb + 32);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3054 "support.c"
INLINE_SUPPORT\
(void)
do_di
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt)
{
#line 70 "mips3264r2.igen"
TRACE_ALU_INPUT0 ();
GPR[rt] = EXTEND32 (SR);
SR &= ~status_IE;
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3067 "support.c"
INLINE_SUPPORT\
(void)
do_dins
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int msb)
{
#line 78 "mips3264r2.igen"
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3080 "support.c"
INLINE_SUPPORT\
(void)
do_dinsm
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int msb)
{
#line 86 "mips3264r2.igen"
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb + 32)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb + 32, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3093 "support.c"
INLINE_SUPPORT\
(void)
do_ei
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt)
{
#line 94 "mips3264r2.igen"
TRACE_ALU_INPUT0 ();
GPR[rt] = EXTEND32 (SR);
SR |= status_IE;
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3106 "support.c"
INLINE_SUPPORT\
(void)
do_ext
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int size)
{
#line 102 "mips3264r2.igen"
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTEND32 (EXTRACTED32 (GPR[rs], lsb + size, lsb));
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3118 "support.c"
INLINE_SUPPORT\
(void)
do_mfhc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 109 "mips3264r2.igen"
check_fpu (SD_);
if (SizeFGR() == 64)
GPR[rt] = EXTEND32 (WORD64HI (FGR[fs]));
else if ((fs & 0x1) == 0)
GPR[rt] = EXTEND32 (FGR[fs + 1]);
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
(long) CIA);
GPR[rt] = EXTEND32 (0xBADF00D);
}
TRACE_ALU_RESULT (GPR[rt]);
}
#line 3141 "support.c"
INLINE_SUPPORT\
(void)
do_mthc1
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int fs)
{
#line 127 "mips3264r2.igen"
check_fpu (SD_);
if (SizeFGR() == 64)
StoreFPR (fs, fmt_uninterpreted_64, SET64HI (GPR[rt]) | VL4_8 (FGR[fs]));
else if ((fs & 0x1) == 0)
StoreFPR (fs + 1, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
(long) CIA);
StoreFPR (fs, fmt_uninterpreted_32, 0xDEADC0DE);
}
TRACE_FP_RESULT (GPR[rt]);
}
#line 3164 "support.c"
INLINE_SUPPORT\
(void)
do_ins
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int msb)
{
#line 145 "mips3264r2.igen"
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] = EXTEND32 (GPR[rt] ^
((GPR[rt] ^ (GPR[rs] << lsb)) & MASK32 (msb, lsb)));
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3178 "support.c"
INLINE_SUPPORT\
(void)
do_dinsu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int lsb, int msb)
{
#line 154 "mips3264r2.igen"
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << (lsb + 32)))
& MASK64 (msb + 32, lsb + 32);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3192 "support.c"
INLINE_SUPPORT\
(void)
do_seb
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 163 "mips3264r2.igen"
TRACE_ALU_INPUT1 (GPR[rt]);
GPR[rd] = EXTEND8 (GPR[rt]);
TRACE_ALU_RESULT1 (GPR[rd]);
}
#line 3204 "support.c"
INLINE_SUPPORT\
(void)
do_seh
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 170 "mips3264r2.igen"
TRACE_ALU_INPUT1 (GPR[rt]);
GPR[rd] = EXTEND16 (GPR[rt]);
TRACE_ALU_RESULT1 (GPR[rd]);
}
#line 3216 "support.c"
INLINE_SUPPORT\
(void)
do_rdhwr
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rd)
{
#line 177 "mips3264r2.igen"
// Return 0 for all hardware registers currently
GPR[rt] = EXTEND32 (0);
TRACE_ALU_RESULT1 (GPR[rt]);
}
#line 3228 "support.c"
INLINE_SUPPORT\
(void)
do_wsbh
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 184 "mips3264r2.igen"
union { uint32_t w; uint16_t h[2]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.w = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
GPR[rd] = EXTEND32 (u.w);
TRACE_ALU_RESULT1 (GPR[rd]);
}
#line 3244 "support.c"
INLINE_SUPPORT\
(const char *)
str_R6COND
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int r6cond)
{
#line 269 "mips3264r6.igen"
switch (r6cond)
{
case FP_R6CMP_SAF:
return "SAF";
case FP_R6CMP_SUN:
return "SUN";
case FP_R6CMP_SOR:
return "SOR";
case FP_R6CMP_SEQ:
return "SEQ";
case FP_R6CMP_SUNE:
return "SUNE";
case FP_R6CMP_SUEQ:
return "SUEQ";
case FP_R6CMP_SNE:
return "SNE";
case FP_R6CMP_SLT:
return "SLT";
case FP_R6CMP_SULT:
return "SULT";
case FP_R6CMP_SLE:
return "SLE";
case FP_R6CMP_SULE:
return "SULE";
case FP_R6CMP_AF:
return "AF";
case FP_R6CMP_UN:
return "UN";
case FP_R6CMP_OR:
return "OR";
case FP_R6CMP_EQ:
return "EQ";
case FP_R6CMP_UNE:
return "UNE";
case FP_R6CMP_UEQ:
return "UEQ";
case FP_R6CMP_NE:
return "NE";
case FP_R6CMP_LT:
return "LT";
case FP_R6CMP_ULT:
return "ULT";
case FP_R6CMP_LE:
return "LE";
case FP_R6CMP_ULE:
return "ULE";
default:
abort ();
}
}
#line 3302 "support.c"
INLINE_SUPPORT\
(address_word)
delayslot16
(SIM_DESC sd, instruction_address cia, int MY_INDEX, address_word nia, address_word target)
{
#line 1037 "m16.igen"
instruction_word delay_insn;
sim_events_slip (SD, 1);
DSPC = CIA; /* save current PC somewhere */
STATE |= simDELAYSLOT;
delay_insn = IMEM16 (nia); /* NOTE: mips16 */
idecode_issue (CPU_, delay_insn, (nia));
STATE &= ~simDELAYSLOT;
return target;
}
#line 3319 "support.c"
INLINE_SUPPORT\
(address_word)
basepc
(SIM_DESC sd, instruction_address cia, int MY_INDEX)
{
#line 1050 "m16.igen"
if (STATE & simDELAYSLOT)
{
return DSPC; /* return saved address of preceeding jmp */
}
else
{
return CIA;
}
}
#line 3336 "support.c"
INLINE_SUPPORT\
(void)
do_save
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int xsregs, int aregs, int ras0s1, int framesize)
{
#line 171 "m16e.igen"
unsigned_word temp;
int args, astatic;
temp = GPR[29];
/* writes are in the same order as the hardware description... */
switch (aregs) {
case 0: case 1: case 2: case 3: case 11:
args = 0;
break;
case 4: case 5: case 6: case 7:
args = 1;
break;
case 8: case 9: case 10:
args = 2;
break;
case 12: case 13:
args = 3;
break;
case 14:
args = 4;
break;
default:
sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
}
if (args > 0) {
do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
if (args > 1) {
do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
if (args > 2) {
do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
if (args > 3) {
do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]);
}
}
}
}
if (ras0s1 & 4)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
switch (xsregs) {
case 7:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
case 6:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
case 5:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
case 4:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
case 3:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
case 2:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
case 1:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
}
if (ras0s1 & 1)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
if (ras0s1 & 2)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
switch (aregs) {
case 0: case 4: case 8: case 12: case 14:
astatic = 0;
break;
case 1: case 5: case 9: case 13:
astatic = 1;
break;
case 2: case 6: case 10:
astatic = 2;
break;
case 3: case 7:
astatic = 3;
break;
case 11:
astatic = 4;
break;
default:
sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
}
if (astatic > 0) {
do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]);
if (astatic > 1) {
do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]);
if (astatic > 2) {
do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]);
if (astatic > 3) {
do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]);
}
}
}
}
GPR[29] -= framesize;
}
#line 3441 "support.c"
INLINE_SUPPORT\
(const char *)
str_MFHI
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int hi)
{
#line 8 "vr.igen"
return hi ? "hi" : "";
}
#line 3451 "support.c"
INLINE_SUPPORT\
(const char *)
str_SAT
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int s)
{
#line 13 "vr.igen"
return s ? "s" : "";
}
#line 3461 "support.c"
INLINE_SUPPORT\
(const char *)
str_UNS
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int u)
{
#line 18 "vr.igen"
return u ? "u" : "";
}
#line 3471 "support.c"
INLINE_SUPPORT\
(void)
do_vr_mul_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p)
{
#line 43 "vr.igen"
uint64_t lhs, x, y, xcut, ycut, product, result;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
x = GPR[rs];
y = GPR[rt];
/* Work out the canonical form of X and Y from their significant bits. */
if (!short_p)
{
/* Normal sign-extension rule for 32-bit operands. */
xcut = EXTEND32 (x);
ycut = EXTEND32 (y);
}
else if (unsigned_p)
{
/* Operands must be zero-extended 16-bit numbers. */
xcut = x & 0xffff;
ycut = y & 0xffff;
}
else
{
/* Likewise but sign-extended. */
xcut = EXTEND16 (x);
ycut = EXTEND16 (y);
}
if (x != xcut || y != ycut)
sim_engine_abort (SD, CPU, CIA,
"invalid multiplication operand at 0x%08lx\n",
(long) CIA);
TRACE_ALU_INPUT2 (x, y);
product = (unsigned_p
? V8_4 (x, 1) * V8_4 (y, 1)
: EXTEND32 (x) * EXTEND32 (y));
result = (subtract_p ? lhs - product : lhs + product);
if (saturate_p)
{
/* Saturate the result to 32 bits. An unsigned, unsaturated
result is zero-extended to 64 bits, but unsigned overflow
causes all 64 bits to be set. */
if (!unsigned_p && (uint64_t) EXTEND32 (result) != result)
result = ((int64_t) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
else if (unsigned_p && (result >> 32) != 0)
result = (uint64_t) 0 - 1;
}
TRACE_ALU_RESULT (result);
if (double_p)
LO = result;
else
{
LO = EXTEND32 (result);
HI = EXTEND32 (VH4_8 (result));
}
if (rd != 0)
GPR[rd] = store_hi_p ? HI : LO;
}
#line 3538 "support.c"
INLINE_SUPPORT\
(void)
do_ph_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int sat)
{
#line 27 "dsp.igen"
int i;
int32_t h0 = 0;
int16_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
if (op == 0) // ADD
h0 = (int32_t)h1 + (int32_t)h2;
else if (op == 1) // SUB
h0 = (int32_t)h1 - (int32_t)h2;
else // MUL
h0 = (int32_t)h1 * (int32_t)h2;
if (h0 > (int32_t)0x7fff || h0 < (int32_t)0xffff8000)
{
if (op == 0 || op == 1) // ADD, SUB
DSPCR |= DSPCR_OUFLAG4;
else if (op == 2) // MUL
DSPCR |= DSPCR_OUFLAG5;
if (sat == 1)
{
if (h0 > (int32_t)0x7fff)
h0 = 0x7fff;
else
h0 = 0x8000;
}
}
result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3580 "support.c"
INLINE_SUPPORT\
(void)
do_w_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op)
{
#line 65 "dsp.igen"
int64_t h0;
int32_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
h1 = (int32_t)v1;
h2 = (int32_t)v2;
if (op == 0) // ADD
h0 = (int64_t)h1 + (int64_t)h2;
else // SUB
h0 = (int64_t)h1 - (int64_t)h2;
if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG4;
if (h0 & 0x100000000LL)
h0 = 0x80000000;
else
h0 = 0x7fffffff;
}
GPR[rd] = EXTEND32 (h0);
}
#line 3609 "support.c"
INLINE_SUPPORT\
(void)
do_qb_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int sat)
{
#line 91 "dsp.igen"
int i;
uint32_t h0;
uint8_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // ADD
h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
h0 = (uint32_t)h1 - (uint32_t)h2;
if (h0 & 0x100)
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
{
if (op == 0) // ADD
h0 = 0xff;
else // SUB
h0 = 0;
}
}
result |= ((uint32_t)((uint8_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3646 "support.c"
INLINE_SUPPORT\
(void)
do_qb_shift
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift, int op)
{
#line 124 "dsp.igen"
int i, j;
uint8_t h0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
h0 = (uint8_t)(v1 & 0xff);
if (op == 0) // left
{
for (j = 7; j >= 8 - shift; j--)
{
if (h0 & (1<> shift;
result |= ((uint32_t)h0 << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3679 "support.c"
INLINE_SUPPORT\
(void)
do_ph_shift
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift, int op, int sat)
{
#line 154 "dsp.igen"
int i, j;
int16_t h0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
int setcond;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
h0 = (int16_t)(v1 & 0xffff);
if (op == 0) // left
{
setcond = 0;
if (h0 & (1<<15))
{
for (j = 14; j >= 15 - shift; j--)
{
if (!(h0 & (1 << j)))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 1;
break;
}
}
}
else
{
for (j = 14; j >= 15 - shift; j--)
{
if (h0 & (1 << j))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 2;
break;
}
}
}
h0 = h0 << shift;
if (sat == 1)
{
if (setcond == 2)
h0 = 0x7fff;
else if (setcond == 1)
h0 = 0x8000;
}
}
else // right
{
if (sat == 1 && shift != 0 && (h0 & (1 << (shift-1))))
h0 = (h0 >> shift) + 1;
else
h0 = h0 >> shift;
}
result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3743 "support.c"
INLINE_SUPPORT\
(void)
do_w_shll
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 213 "dsp.igen"
int i;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
int setcond = 0;
if (v1 & (1 << 31))
{
for (i = 30; i >= 31 - shift; i--)
{
if (!(v1 & (1 << i)))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 1;
break;
}
}
}
else
{
for (i = 30; i >= 31 - shift; i--)
{
if (v1 & (1 << i))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 2;
break;
}
}
}
if (setcond == 2)
result = 0x7fffffff;
else if (setcond == 1)
result = 0x80000000;
else
result = v1 << shift;
GPR[rd] = EXTEND32 (result);
}
#line 3787 "support.c"
INLINE_SUPPORT\
(void)
do_ph_s_absq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 252 "dsp.igen"
int i;
int16_t h0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
h0 = (int16_t)(v1 & 0xffff);
if (h0 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fff;
}
else if (h0 & 0x8000)
h0 = -h0;
result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3813 "support.c"
INLINE_SUPPORT\
(void)
do_w_s_absq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 273 "dsp.igen"
uint32_t v1 = GPR[rt];
int32_t h0 = (int32_t)v1;
if (h0 == (int32_t)0x80000000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fffffff;
}
else if (h0 & 0x80000000)
h0 = -h0;
GPR[rd] = EXTEND32 (h0);
}
#line 3832 "support.c"
INLINE_SUPPORT\
(void)
do_qb_s_absq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 287 "dsp.igen"
int i;
int8_t q0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
q0 = (int8_t)(v1 & 0xff);
if (q0 == (int8_t)0x80)
{
DSPCR |= DSPCR_OUFLAG4;
q0 = 0x7f;
}
else if (q0 & 0x80)
q0 = -q0;
result |= ((uint32_t)((uint8_t)q0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 3858 "support.c"
INLINE_SUPPORT\
(void)
do_addsc
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 308 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint64_t h0;
h0 = (uint64_t)v1 + (uint64_t)v2;
if (h0 & 0x100000000LL)
DSPCR |= DSPCR_CARRY;
GPR[rd] = EXTEND32 (h0);
}
#line 3874 "support.c"
INLINE_SUPPORT\
(void)
do_addwc
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 319 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint64_t h0;
int32_t h1 = (int32_t) v1;
int32_t h2 = (int32_t) v2;
h0 = (int64_t)h1 + (int64_t)h2
+ (int64_t)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);
if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
DSPCR |= DSPCR_OUFLAG4;
GPR[rd] = EXTEND32 (h0);
}
#line 3893 "support.c"
INLINE_SUPPORT\
(void)
do_bitrev
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt)
{
#line 333 "dsp.igen"
int i;
uint32_t v1 = GPR[rt];
uint32_t h1 = 0;
for (i = 0; i < 16; i++)
{
if (v1 & (1 << i))
h1 |= (1 << (15 - i));
}
GPR[rd] = EXTEND32 (h1);
}
#line 3911 "support.c"
INLINE_SUPPORT\
(void)
do_extpv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int rs, int op)
{
#line 347 "dsp.igen"
uint32_t size = GPR[rs] & 0x1f;
do_extp (SD_, rt, ac, size, op);
}
#line 3922 "support.c"
INLINE_SUPPORT\
(void)
do_extrv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int rs, int op)
{
#line 354 "dsp.igen"
uint32_t shift = GPR[rs] & 0x1f;
do_w_extr (SD_, rt, ac, shift, op);
}
#line 3933 "support.c"
INLINE_SUPPORT\
(void)
do_extrv_s_h
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int rs)
{
#line 360 "dsp.igen"
uint32_t shift = GPR[rs] & 0x1f;
do_h_extr (SD_, rt, ac, shift);
}
#line 3944 "support.c"
INLINE_SUPPORT\
(void)
do_insv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs)
{
#line 366 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
uint32_t size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;
uint32_t mask1, mask2, mask3, result;
if (size < 32)
mask1 = (1 << size) - 1;
else
mask1 = 0xffffffff;
mask2 = (1 << pos) - 1;
if (pos + size < 32)
mask3 = ~((1 << (pos + size)) - 1);
else
mask3 = 0;
result = (v2 & mask3) | ((v1 & mask1) << pos) | (v2 & mask2);
GPR[rt] = EXTEND32 (result);
}
#line 3969 "support.c"
INLINE_SUPPORT\
(void)
do_lxx
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int base, int index, int op)
{
#line 387 "dsp.igen"
if (op == 0)
GPR[rd] = do_load (SD_, AccessLength_BYTE, GPR[base], GPR[index]);
else if (op == 1)
GPR[rd] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base], GPR[index]));
else if (op == 2)
GPR[rd] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
}
#line 3984 "support.c"
INLINE_SUPPORT\
(void)
do_modsub
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 397 "dsp.igen"
uint32_t result = 0;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t decr = v2 & 0xff;
uint32_t lastindex = (v2 & 0xffff00) >> 8;
if (v1 == 0)
result = lastindex;
else
result = v1 - decr;
GPR[rd] = EXTEND32 (result);
}
#line 4003 "support.c"
INLINE_SUPPORT\
(void)
do_mthlip
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int ac)
{
#line 411 "dsp.igen"
uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
DSPHI(ac) = DSPLO(ac);
DSPLO(ac) = GPR[rs];
if (pos >= 32)
Unpredictable ();
else
pos += 32;
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
}
#line 4021 "support.c"
INLINE_SUPPORT\
(void)
do_mulsaq_s_w_ph
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 424 "dsp.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (int32_t) 0x7fffffff;
}
else
result = ((int32_t)h1 * (int32_t)h2) << 1;
if (i == 0)
prod -= (int64_t) result;
else
prod += (int64_t) result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 4057 "support.c"
INLINE_SUPPORT\
(void)
do_ph_packrl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 455 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
GPR[rd] = EXTEND32 ((v1 << 16) + (v2 >> 16));
}
#line 4070 "support.c"
INLINE_SUPPORT\
(void)
do_qb_pick
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 463 "dsp.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint8_t h1, h2;
uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
result |= (uint32_t)(h1 << i);
else
result |= (uint32_t)(h2 << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 4094 "support.c"
INLINE_SUPPORT\
(void)
do_ph_pick
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 482 "dsp.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint16_t h1, h2;
uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
h1 = (uint16_t)(v1 & 0xffff);
h2 = (uint16_t)(v2 & 0xffff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
result |= (uint32_t)(h1 << i);
else
result |= (uint32_t)(h2 << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 4118 "support.c"
INLINE_SUPPORT\
(void)
do_qb_ph_precequ
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int op)
{
#line 502 "dsp.igen"
uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7);
else if (op == 1)
GPR[rd] = EXTEND32 ((v1 & 0xff0000) << 7) | ((v1 & 0xff) << 7);
else if (op == 2)
GPR[rd] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff0000) >> 9);
else if (op == 3)
GPR[rd] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff00) >> 1);
}
#line 4136 "support.c"
INLINE_SUPPORT\
(void)
do_qb_ph_preceu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int op)
{
#line 516 "dsp.igen"
uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff);
else if (op == 1)
GPR[rd] = EXTEND32 ((v1 & 0xff0000) | (v1 & 0xff));
else if (op == 2)
GPR[rd] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff0000) >> 16);
else if (op == 3)
GPR[rd] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff00) >> 8);
}
#line 4154 "support.c"
INLINE_SUPPORT\
(void)
do_w_preceq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int op)
{
#line 530 "dsp.igen"
uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 (v1 & 0xffff0000);
else if (op == 1)
GPR[rd] = EXTEND32 ((v1 & 0xffff) << 16);
}
#line 4168 "support.c"
INLINE_SUPPORT\
(void)
do_w_ph_precrq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 539 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t tempu = (v1 & 0xffff0000) >> 16;
uint32_t tempv = (v2 & 0xffff0000) >> 16;
GPR[rd] = EXTEND32 ((tempu << 16) | tempv);
}
#line 4182 "support.c"
INLINE_SUPPORT\
(void)
do_ph_qb_precrq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int sat)
{
#line 549 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t tempu = 0, tempv = 0, tempw = 0, tempx = 0;
if (sat == 0)
{
tempu = (v1 & 0xff000000) >> 24;
tempv = (v1 & 0xff00) >> 8;
tempw = (v2 & 0xff000000) >> 24;
tempx = (v2 & 0xff00) >> 8;
}
else if (sat == 1)
{
if (v1 & 0x80000000)
{
DSPCR |= DSPCR_OUFLAG6;
tempu = 0;
}
else if (!(v1 & 0x80000000) && ((v1 >> 16) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempu = 0xff;
}
else
tempu = (v1 & 0x7f800000) >> 23;
if (v1 & 0x8000)
{
DSPCR |= DSPCR_OUFLAG6;
tempv = 0;
}
else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempv = 0xff;
}
else
tempv = (v1 & 0x7f80) >> 7;
if (v2 & 0x80000000)
{
DSPCR |= DSPCR_OUFLAG6;
tempw = 0;
}
else if (!(v2 & 0x80000000) && ((v2 >> 16) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempw = 0xff;
}
else
tempw = (v2 & 0x7f800000) >> 23;
if (v2 & 0x8000)
{
DSPCR |= DSPCR_OUFLAG6;
tempx = 0;
}
else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempx = 0xff;
}
else
tempx = (v2 & 0x7f80) >> 7;
}
GPR[rd] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
}
#line 4253 "support.c"
INLINE_SUPPORT\
(void)
do_w_ph_rs_precrq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 615 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int32_t h1 = (int32_t)v1;
int32_t h2 = (int32_t)v2;
int64_t temp1 = (int64_t)h1 + (int64_t)0x8000;
int32_t temp2;
int64_t temp3 = (int64_t)h2 + (int64_t)0x8000;
int32_t temp4;
if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp2 = 0x7fff;
}
else
temp2 = (int32_t)((temp1 & 0xffff0000) >> 16);
if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp4 = 0x7fff;
}
else
temp4 = (int32_t)((temp3 & 0xffff0000) >> 16);
GPR[rd] = EXTEND32 ((temp2 << 16) | temp4);
}
#line 4285 "support.c"
INLINE_SUPPORT\
(void)
do_qb_w_raddu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs)
{
#line 642 "dsp.igen"
int i;
uint8_t h0;
uint32_t v1 = GPR[rs];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
h0 = (uint8_t)(v1 & 0xff);
result += (uint32_t)h0;
}
GPR[rd] = EXTEND32 (result);
}
#line 4304 "support.c"
INLINE_SUPPORT\
(void)
do_rddsp
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int mask)
{
#line 656 "dsp.igen"
uint32_t result = 0;
if (mask & 0x1)
{
result &= (~DSPCR_POS_SMASK);
result |= (DSPCR & DSPCR_POS_SMASK);
}
if (mask & 0x2)
{
result &= (~DSPCR_SCOUNT_SMASK);
result |= (DSPCR & DSPCR_SCOUNT_SMASK);
}
if (mask & 0x4)
{
result &= (~DSPCR_CARRY_SMASK);
result |= (DSPCR & DSPCR_CARRY_SMASK);
}
if (mask & 0x8)
{
result &= (~DSPCR_OUFLAG_SMASK);
result |= (DSPCR & DSPCR_OUFLAG_SMASK);
}
if (mask & 0x10)
{
result &= (~DSPCR_CCOND_SMASK);
result |= (DSPCR & DSPCR_CCOND_SMASK);
}
if (mask & 0x20)
{
result &= (~DSPCR_EFI_SMASK);
result |= (DSPCR & DSPCR_EFI_SMASK);
}
GPR[rd] = EXTEND32 (result);
}
#line 4345 "support.c"
INLINE_SUPPORT\
(void)
do_repl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int p2, int op)
{
#line 693 "dsp.igen"
if (op == 0)
GPR[rd] = EXTEND32 ((p2 << 24) | (p2 << 16) | (p2 << 8) | p2);
else if (op == 1)
{
uint32_t v1 = GPR[p2] & 0xff;
GPR[rd] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1);
}
else if (op == 2)
{
int32_t v1 = p2;
if (v1 & 0x200)
v1 |= 0xfffffc00;
GPR[rd] = EXTEND32 ((v1 << 16) | (v1 & 0xffff));
}
else if (op == 3)
{
uint32_t v1 = GPR[p2];
v1 = v1 & 0xffff;
GPR[rd] = EXTEND32 ((v1 << 16) | v1);
}
}
#line 4374 "support.c"
INLINE_SUPPORT\
(void)
do_shilov
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs)
{
#line 717 "dsp.igen"
int32_t shift = GPR[rs] & 0x3f;
do_shilo (SD_, ac, shift);
}
#line 4385 "support.c"
INLINE_SUPPORT\
(void)
do_ph_shl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs, int op, int sat)
{
#line 725 "dsp.igen"
uint32_t shift = GPR[rs] & 0xf;
do_ph_shift (SD_, rd, rt, shift, op, sat);
}
#line 4396 "support.c"
INLINE_SUPPORT\
(void)
do_qb_shl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs, int op)
{
#line 732 "dsp.igen"
uint32_t shift = GPR[rs] & 0x7;
do_qb_shift (SD_, rd, rt, shift, op);
}
#line 4407 "support.c"
INLINE_SUPPORT\
(void)
do_w_s_shllv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs)
{
#line 738 "dsp.igen"
uint32_t shift = GPR[rs] & 0x1f;
do_w_shll (SD_, rd, rt, shift);
}
#line 4418 "support.c"
INLINE_SUPPORT\
(void)
do_ph_shrlv
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs)
{
#line 744 "dsp.igen"
uint32_t shift = GPR[rs] & 0xf;
do_ph_shrl (SD_, rd, rt, shift);
}
#line 4429 "support.c"
INLINE_SUPPORT\
(void)
do_w_r_shrav
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs)
{
#line 750 "dsp.igen"
uint32_t shift = GPR[rs] & 0x1f;
do_w_shra (SD_, rd, rt, shift);
}
#line 4440 "support.c"
INLINE_SUPPORT\
(void)
do_wrdsp
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int mask)
{
#line 756 "dsp.igen"
uint32_t v1 = GPR[rs];
if (mask & 0x1)
{
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= (v1 & DSPCR_POS_SMASK);
}
if (mask & 0x2)
{
DSPCR &= (~DSPCR_SCOUNT_SMASK);
DSPCR |= (v1 & DSPCR_SCOUNT_SMASK);
}
if (mask & 0x4)
{
DSPCR &= (~DSPCR_CARRY_SMASK);
DSPCR |= (v1 & DSPCR_CARRY_SMASK);
}
if (mask & 0x8)
{
DSPCR &= (~DSPCR_OUFLAG_SMASK);
DSPCR |= (v1 & DSPCR_OUFLAG_SMASK);
}
if (mask & 0x10)
{
DSPCR &= (~DSPCR_CCOND_SMASK);
DSPCR |= (v1 & DSPCR_CCOND_SMASK);
}
if (mask & 0x20)
{
DSPCR &= (~DSPCR_EFI_SMASK);
DSPCR |= (v1 & DSPCR_EFI_SMASK);
}
}
#line 4480 "support.c"
INLINE_SUPPORT\
(void)
do_qb_shrav
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int rs, int round)
{
#line 792 "dsp.igen"
uint32_t shift = GPR[rs] & 0x7;
do_qb_shra (SD_, rd, rt, shift, round);
}
#line 4491 "support.c"
INLINE_SUPPORT\
(void)
do_append
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int sa)
{
#line 798 "dsp.igen"
uint32_t v0 = GPR[rs];
uint32_t v1 = GPR[rt];
uint32_t result;
uint32_t mask = (1 << sa) - 1;
result = (v1 << sa) | (v0 & mask);
GPR[rt] = EXTEND32 (result);
}
#line 4506 "support.c"
INLINE_SUPPORT\
(void)
do_balign
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int bp)
{
#line 808 "dsp.igen"
uint32_t v0 = GPR[rs];
uint32_t v1 = GPR[rt];
uint32_t result;
if (bp == 0)
result = v1;
else
result = (v1 << 8 * bp) | (v0 >> 8 * (4 - bp));
GPR[rt] = EXTEND32 (result);
}
#line 4523 "support.c"
INLINE_SUPPORT\
(void)
do_ph_w_mulsa
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt)
{
#line 820 "dsp.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
result = (int32_t)h1 * (int32_t)h2;
if (i == 0)
prod -= (int64_t) result;
else
prod += (int64_t) result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 4553 "support.c"
INLINE_SUPPORT\
(void)
do_ph_qb_precr
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt)
{
#line 845 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t tempu = (v1 & 0xff0000) >> 16;
uint32_t tempv = (v1 & 0xff);
uint32_t tempw = (v2 & 0xff0000) >> 16;
uint32_t tempx = (v2 & 0xff);
GPR[rd] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
}
#line 4569 "support.c"
INLINE_SUPPORT\
(void)
do_prepend
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int sa)
{
#line 856 "dsp.igen"
uint32_t v0 = GPR[rs];
uint32_t v1 = GPR[rt];
uint32_t result;
if (sa == 0)
result = v1;
else
result = (v0 << (32 - sa)) | (v1 >> sa);
GPR[rt] = EXTEND32 (result);
}
#line 4586 "support.c"
INLINE_SUPPORT\
(void)
do_w_shra
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 868 "dsp.igen"
uint32_t result = GPR[rt];
int32_t h0 = (int32_t)result;
if (shift != 0 && (h0 & (1 << (shift-1))))
h0 = (h0 >> shift) + 1;
else
h0 = h0 >> shift;
GPR[rd] = EXTEND32 (h0);
}
#line 4602 "support.c"
INLINE_SUPPORT\
(void)
do_qb_muleu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int loc)
{
#line 1202 "dsp.igen"
int i;
uint32_t result = 0;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint16_t h1, h2;
uint32_t prod;
if (loc == 0)
v1 >>= 16;
for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16)
{
h1 = (uint16_t)(v1 & 0xff);
h2 = (uint16_t)(v2 & 0xffff);
prod = (uint32_t)h1 * (uint32_t)h2;
if (prod > 0xffff)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0xffff;
}
result |= ((uint32_t)prod << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 4632 "support.c"
INLINE_SUPPORT\
(void)
do_ph_mulq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int round)
{
#line 1242 "dsp.igen"
int i;
uint32_t result = 0;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t prod;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
{
prod = ((int32_t)h1 * (int32_t)h2) << 1;
if (round == 1)
prod += (int32_t)0x8000;
}
result |= (((uint32_t)prod >> 16) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 4665 "support.c"
INLINE_SUPPORT\
(void)
do_ph_muleq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int loc)
{
#line 1278 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t prod;
if (loc == 0)
{
h1 = (int16_t)(v1 >> 16);
h2 = (int16_t)(v2 >> 16);
}
else
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
}
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
prod = ((int32_t)h1 * (int32_t)h2) << 1;
GPR[rd] = EXTEND32 (prod);
}
#line 4696 "support.c"
INLINE_SUPPORT\
(void)
do_qb_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op, int loc)
{
#line 1320 "dsp.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint8_t h1, h2;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
if (loc == 0)
{
v1 >>= 16;
v2 >>= 16;
}
for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // DPAU
prod += (uint64_t)h1 * (uint64_t)h2;
else // DPSU
prod -= (uint64_t)h1 * (uint64_t)h2;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 4728 "support.c"
INLINE_SUPPORT\
(void)
do_ph_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op)
{
#line 1376 "dsp.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (int32_t)0x7fffffff;
}
else
result = ((int32_t)h1 * (int32_t)h2) << 1;
if (op == 0) // DPAQ
prod += (int64_t)result;
else // DPSQ
prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 4764 "support.c"
INLINE_SUPPORT\
(void)
do_w_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op)
{
#line 1429 "dsp.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int32_t h1, h2;
int64_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint32_t resultlo;
uint32_t resulthi;
uint32_t carry;
uint64_t temp1;
int64_t temp2;
h1 = (int32_t) v1;
h2 = (int32_t) v2;
if (h1 == 0x80000000 && h2 == 0x80000000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (int64_t) 0x7fffffffffffffffLL;
}
else
result = ((int64_t)h1 * (int64_t)h2) << 1;
resultlo = (uint32_t)(result);
resulthi = (uint32_t)(result >> 32);
if (op ==0) // DPAQ
{
temp1 = (uint64_t)lo + (uint64_t)resultlo;
carry = (uint32_t)((temp1 >> 32) & 1);
temp2 = (int64_t)((int32_t)hi) + (int64_t)((int32_t)resulthi) +
(int64_t)((int32_t)carry);
}
else // DPSQ
{
temp1 = (uint64_t)lo - (uint64_t)resultlo;
carry = (uint32_t)((temp1 >> 32) & 1);
temp2 = (int64_t)((int32_t)hi) - (int64_t)((int32_t)resulthi) -
(int64_t)((int32_t)carry);
}
if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
if (temp2 & 0x100000000LL)
{
DSPLO(ac) = EXTEND32 (0x00000000);
DSPHI(ac) = EXTEND32 (0x80000000);
}
else
{
DSPLO(ac) = EXTEND32 (0xffffffff);
DSPHI(ac) = EXTEND32 (0x7fffffff);
}
}
else
{
DSPLO(ac) = EXTEND32 (temp1);
DSPHI(ac) = EXTEND32 (temp2);
}
}
#line 4828 "support.c"
INLINE_SUPPORT\
(void)
do_ph_maq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op, int loc)
{
#line 1504 "dsp.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
if (loc == 0)
{
h1 = (int16_t)(v1 >> 16);
h2 = (int16_t)(v2 >> 16);
}
else
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
}
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (int32_t)0x7fffffff;
}
else
result = ((int32_t)h1 * (int32_t)h2) << 1;
prod += (int64_t)result;
if (op == 1) // MAQ_SA
{
if (prod & 0x8000000000000000LL)
{
for (i = 62; i >= 31; i--)
{
if (!(prod & ((int64_t)1 << i)))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0xffffffff80000000LL;
break;
}
}
}
else
{
for (i = 62; i >= 31; i--)
{
if (prod & ((int64_t)1 << i))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0x7fffffff;
break;
}
}
}
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 4892 "support.c"
INLINE_SUPPORT\
(void)
do_qb_cmpu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int op)
{
#line 1634 "dsp.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint8_t h1, h2;
uint32_t mask;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
else if (op == 1) // LT
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
else // LE
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
}
}
#line 4919 "support.c"
INLINE_SUPPORT\
(void)
do_qb_cmpgu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op)
{
#line 1678 "dsp.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint8_t h1, h2;
uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // EQ
result |= ((h1 == h2) << j);
else if (op == 1) // LT
result |= ((h1 < h2) << j);
else // LE
result |= ((h1 <= h2) << j);
}
GPR[rd] = EXTEND32 (result);
}
#line 4945 "support.c"
INLINE_SUPPORT\
(void)
do_ph_cmpu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rs, int rt, int op)
{
#line 1721 "dsp.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
uint32_t mask;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
else if (op == 1) // LT
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
else // LE
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
}
}
#line 4972 "support.c"
INLINE_SUPPORT\
(void)
do_w_extr
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int shift, int op)
{
#line 1786 "dsp.igen"
int i;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
int64_t result = (int64_t)prod;
int setcond = 0;
if (!(prod & 0x8000000000000000LL))
{
for (i = 62; i >= (shift + 31); i--)
{
if (prod & ((uint64_t)1 << i))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 1;
break;
}
}
if (((prod >> (shift - 1)) & 0xffffffffLL) == 0xffffffffLL)
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 1;
}
}
else
{
for (i = 62; i >= (shift + 31); i--)
{
if (!(prod & ((uint64_t)1 << i)))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 2;
break;
}
}
}
if (op == 0) // EXTR
result = result >> shift;
else if (op == 1) // EXTR_R
{
if (shift != 0)
result = ((result >> (shift - 1)) + 1) >> 1;
else
result = result >> shift;
}
else // EXTR_RS
{
if (setcond == 1)
result = 0x7fffffff;
else if (setcond == 2)
result = 0x80000000;
else
{
if (shift != 0)
result = ((result >> (shift - 1)) + 1) >> 1;
else
result = result >> shift;
}
}
GPR[rt] = EXTEND32 (result);
}
#line 5040 "support.c"
INLINE_SUPPORT\
(void)
do_h_extr
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int shift)
{
#line 1891 "dsp.igen"
int i;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
int64_t result = (int64_t)prod;
int64_t value = 0xffffffffffff8000LL;
result >>= shift;
if (result > 0x7fff)
{
result = 0x7fff;
DSPCR |= DSPCR_OUFLAG7;
}
else if (result < value)
{
result = value;
DSPCR |= DSPCR_OUFLAG7;
}
GPR[rt] = EXTEND32 (result);
}
#line 5067 "support.c"
INLINE_SUPPORT\
(void)
do_extp
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int ac, int size, int op)
{
#line 1928 "dsp.igen"
int32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
uint64_t result = 0;
if (pos - (size + 1) >= -1)
{
prod >>= (pos - size);
result = prod & (((uint64_t)1 << (size + 1)) - 1);
DSPCR &= (~DSPCR_EFI_SMASK);
if (op == 1) // EXTPDP
{
if (pos - (size + 1) >= 0)
{
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= ((pos - (size + 1)) & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
}
else if (pos - (size + 1) == -1)
{
DSPCR |= DSPCR_POS_SMASK;
}
}
}
else
{
DSPCR |= DSPCR_EFI;
Unpredictable ();
}
GPR[rt] = EXTEND32 (result);
}
#line 5105 "support.c"
INLINE_SUPPORT\
(void)
do_shilo
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int shift)
{
#line 1989 "dsp.igen"
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
if (shift > 31)
shift = shift - 64;
if (shift >= 0)
prod >>= shift;
else
prod <<= (-shift);
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 5125 "support.c"
INLINE_SUPPORT\
(void)
do_u_ph_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int sat)
{
#line 28 "dsp2.igen"
int i;
uint32_t h0;
uint16_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (uint16_t)(v1 & 0xffff);
h2 = (uint16_t)(v2 & 0xffff);
if (op == 0) // ADD
h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
h0 = (uint32_t)h1 - (uint32_t)h2;
if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
h0 = 0xffff;
}
else if (op == 1 && h1 < h2) // SUB SAT
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
h0 = 0x0;
}
result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 5163 "support.c"
INLINE_SUPPORT\
(void)
do_uh_qb_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int round)
{
#line 63 "dsp2.igen"
int i;
uint32_t h0;
uint8_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // ADD
h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
h0 = (uint32_t)h1 - (uint32_t)h2;
if (round == 1)
h0 = (h0 + 1) >> 1;
else
h0 = h0 >> 1;
result |= ((uint32_t)((uint8_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 5193 "support.c"
INLINE_SUPPORT\
(void)
do_qb_cmpgdu
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op)
{
#line 89 "dsp2.igen"
int i, j;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint8_t h1, h2;
uint32_t result = 0;
uint32_t mask;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (uint8_t)(v1 & 0xff);
h2 = (uint8_t)(v2 & 0xff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
{
result |= ((h1 == h2) << j);
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
}
else if (op == 1) // LT
{
result |= ((h1 < h2) << j);
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
}
else // LE
{
result |= ((h1 <= h2) << j);
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
}
}
GPR[rd] = EXTEND32 (result);
}
#line 5231 "support.c"
INLINE_SUPPORT\
(void)
do_w_ph_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op)
{
#line 123 "dsp2.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
result = (int32_t)h1 * (int32_t)h2;
if (op == 0) // DPA
prod += (int64_t)result;
else // DPS
prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 5260 "support.c"
INLINE_SUPPORT\
(void)
do_w_mulq
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int round)
{
#line 148 "dsp2.igen"
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int32_t w1, w2;
int64_t prod;
uint32_t result;
w1 = (int32_t) v1;
w2 = (int32_t) v2;
if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
{
prod = ((int64_t) w1 * (int64_t) w2) << 1;
if (round == 1)
prod += 0x0000000080000000LL;
prod = prod >> 32;
}
result = (uint32_t) prod;
GPR[rd] = EXTEND32 (result);
}
#line 5290 "support.c"
INLINE_SUPPORT\
(void)
do_precr_sra
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rt, int rs, int sa, int round)
{
#line 174 "dsp2.igen"
uint32_t v1 = GPR[rt];
uint32_t v2 = GPR[rs];
int32_t w1 = (int32_t) v1;
int32_t w2 = (int32_t) v2;
int32_t result;
if (sa != 0)
{
if (round == 1 && (w1 & (1 << (sa - 1))))
w1 = (w1 >> sa) + 1;
else
w1 = w1 >> sa;
if (round == 1 && (w2 & (1 << (sa - 1))))
w2 = (w2 >> sa) + 1;
else
w2 = w2 >> sa;
}
result = (w1 << 16) | (w2 & 0xffff);
GPR[rt] = EXTEND32 (result);
}
#line 5318 "support.c"
INLINE_SUPPORT\
(void)
do_qb_shra
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift, int round)
{
#line 198 "dsp2.igen"
int i, j;
int8_t q0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
q0 = (int8_t)(v1 & 0xff);
if (shift != 0)
{
if (round == 1 && (q0 & (1 << (shift - 1))))
q0 = (q0 >> shift) + 1;
else
q0 = q0 >> shift;
}
result |= ((uint32_t)((uint8_t)q0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 5344 "support.c"
INLINE_SUPPORT\
(void)
do_ph_shrl
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rt, int shift)
{
#line 219 "dsp2.igen"
int i, j;
uint16_t h0;
uint32_t v1 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
h0 = (uint16_t)(v1 & 0xffff);
h0 = h0 >> shift;
result |= ((uint32_t)h0 << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 5364 "support.c"
INLINE_SUPPORT\
(void)
do_qh_ph_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int round)
{
#line 236 "dsp2.igen"
int i;
int32_t h0;
int16_t h1, h2;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)(v2 & 0xffff);
if (op == 0) // ADD
h0 = (int32_t)h1 + (int32_t)h2;
else // SUB
h0 = (int32_t)h1 - (int32_t)h2;
if (round == 1)
h0 = (h0 + 1) >> 1;
else
h0 = h0 >> 1;
result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
#line 5394 "support.c"
INLINE_SUPPORT\
(void)
do_qh_w_op
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int rd, int rs, int rt, int op, int round)
{
#line 263 "dsp2.igen"
int i;
int64_t v0;
int32_t v1 = (int32_t)GPR[rs];
int32_t v2 = (int32_t)GPR[rt];
if (op == 0) // ADD
v0 = (int64_t)v1 + (int64_t)v2;
else // SUB
v0 = (int64_t)v1 - (int64_t)v2;
if (round == 1)
v0 = (v0 + 1) >> 1;
else
v0 = v0 >> 1;
GPR[rd] = EXTEND32 (v0);
}
#line 5416 "support.c"
INLINE_SUPPORT\
(void)
do_x_w_ph_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op)
{
#line 281 "dsp2.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)((v2 & 0xffff0000) >> 16);
result = (int32_t)h1 * (int32_t)h2;
if (op == 0) // DPAX
prod += (int64_t)result;
else // DPSX
prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 5445 "support.c"
INLINE_SUPPORT\
(void)
do_qx_w_ph_dot_product
(SIM_DESC sd, instruction_address cia, int MY_INDEX, int ac, int rs, int rt, int op, int sat)
{
#line 307 "dsp2.igen"
int i;
uint32_t v1 = GPR[rs];
uint32_t v2 = GPR[rt];
int16_t h1, h2;
int32_t result;
uint32_t lo = DSPLO(ac);
uint32_t hi = DSPHI(ac);
int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
int64_t max, min;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
{
h1 = (int16_t)(v1 & 0xffff);
h2 = (int16_t)((v2 & 0xffff0000) >> 16);
if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = 0x7fffffff;
}
else
result = ((int32_t)h1 * (int32_t)h2) << 1;
if (op == 0) // DPAQX
prod += (int64_t)result;
else // DPSQX
prod -= (int64_t)result;
}
// Saturation on the accumulator.
if (sat == 1)
{
max = (int64_t) 0x7fffffffLL;
min = (int64_t) 0xffffffff80000000LL;
if (prod > max)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = max;
}
else if (prod < min)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = min;
}
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
#line 5497 "support.c"
#endif /* _SUPPORT_C_*/