86 lines
1.4 KiB
ArmAsm
86 lines
1.4 KiB
ArmAsm
//Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp
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// Spec Reference: ldimmhalf dreg hi
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0.H = 0x0001;
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R1.H = 0x0003;
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R2.H = 0x0005;
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R3.H = 0x0007;
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R4.H = 0x0009;
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R5.H = 0x000b;
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R6.H = 0x000d;
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R7.H = 0x000f;
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CHECKREG r0, 0x0001FFFF;
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CHECKREG r1, 0x0003FFFF;
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CHECKREG r2, 0x0005FFFF;
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CHECKREG r3, 0x0007FFFF;
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CHECKREG r4, 0x0009FFFF;
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CHECKREG r5, 0x000bFFFF;
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CHECKREG r6, 0x000dFFFF;
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CHECKREG r7, 0x000fFFFF;
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R0.H = 0x0020;
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R1.H = 0x0040;
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R2.H = 0x0060;
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R3.H = 0x0080;
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R4.H = 0x00a0;
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R5.H = 0x00b0;
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R6.H = 0x00c0;
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R7.H = 0x00d0;
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CHECKREG r0, 0x0020FFFF;
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CHECKREG r1, 0x0040FFFF;
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CHECKREG r2, 0x0060FFFF;
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CHECKREG r3, 0x0080FFFF;
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CHECKREG r4, 0x00a0FFFF;
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CHECKREG r5, 0x00b0FFFF;
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CHECKREG r6, 0x00c0FFFF;
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CHECKREG r7, 0x00d0FFFF;
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R0.H = 0x0100;
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R1.H = 0x0200;
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R2.H = 0x0300;
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R3.H = 0x0400;
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R4.H = 0x0500;
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R5.H = 0x0600;
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R6.H = 0x0700;
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R7.H = 0x0800;
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CHECKREG r0, 0x0100FFFF;
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CHECKREG r1, 0x0200FFFF;
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CHECKREG r2, 0x0300FFFF;
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CHECKREG r3, 0x0400FFFF;
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CHECKREG r4, 0x0500FFFF;
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CHECKREG r5, 0x0600FFFF;
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CHECKREG r6, 0x0700FFFF;
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CHECKREG r7, 0x0800FFFF;
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R0 = 0;
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R1 = 0;
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R2 = 0;
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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R0.H = 0x7fff;
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R1.H = 0x7ffe;
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R2.H = 32767;
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R3.H = 32766;
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R4.H = -32768;
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R5.H = -32767;
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CHECKREG r0, 0x7fff0000;
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CHECKREG r1, 0x7ffe0000;
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CHECKREG r2, 0x7fff0000;
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CHECKREG r3, 0x7ffe0000;
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CHECKREG r4, 0x80000000;
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CHECKREG r5, 0x80010000;
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pass
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