213 lines
3.7 KiB
ArmAsm
213 lines
3.7 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp
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// Spec Reference: ldimmhalf p i b m l
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# mach: bfin
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.include "testutils.inc"
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start
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// set all reg=-1
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//p0 =0x0123;
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P1 = 0x1234 (X);
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P2 = 0x2345 (X);
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P3 = 0x3456 (X);
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P4 = 0x4567 (X);
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P5 = 0x5678 (X);
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FP = 0x6789 (X);
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SP = 0x789a (X);
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//CHECKREG p0, 0x00000123;
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CHECKREG p1, 0x00001234;
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CHECKREG p2, 0x00002345;
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CHECKREG p3, 0x00003456;
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CHECKREG p4, 0x00004567;
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CHECKREG p5, 0x00005678;
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CHECKREG fp, 0x00006789;
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CHECKREG sp, 0x0000789A;
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//p0 = -32768;
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P1 = -32768 (X);
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P2 = -2222 (X);
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P3 = -3333 (X);
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P4 = -4444 (X);
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P5 = -5555 (X);
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FP = -6666 (X);
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SP = -7777 (X);
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//CHECKREG r0, 0xFFFF8000;
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CHECKREG p1, 0xFFFF8000;
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CHECKREG p2, 0xFFFFF752;
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CHECKREG p3, 0xFFFFF2FB;
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CHECKREG p4, 0xFFFFEEA4;
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CHECKREG p5, 0xFFFFEA4D;
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CHECKREG fp, 0xFFFFE5F6;
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CHECKREG sp, 0xFFFFE19F;
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//p0 =0x0123;
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P1 = 0x7abc (X);
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P2 = 0x6def (X);
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P3 = 0x5f56 (X);
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P4 = 0x7dd7 (X);
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P5 = 0x4abd (X);
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FP = 0x7fff (X);
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SP = 0x7ffa (X);
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//CHECKREG p0, 0x00000123;
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CHECKREG p1, 0x00007abc;
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CHECKREG p2, 0x00006def;
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CHECKREG p3, 0x00005f56;
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CHECKREG p4, 0x00007dd7;
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CHECKREG p5, 0x00004abd;
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CHECKREG fp, 0x00007fff;
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CHECKREG sp, 0x00007ffa;
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I0 = 0x0123 (X);
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I1 = 0x1234 (X);
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I2 = 0x2345 (X);
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I3 = 0x3456 (X);
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B0 = 0x0567 (X);
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B1 = 0x1678 (X);
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B2 = 0x2789 (X);
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B3 = 0x389a (X);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00000123;
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CHECKREG r1, 0x00001234;
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CHECKREG r2, 0x00002345;
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CHECKREG r3, 0x00003456;
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CHECKREG r4, 0x00000567;
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CHECKREG r5, 0x00001678;
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CHECKREG r6, 0x00002789;
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CHECKREG r7, 0x0000389A;
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I0 = -32768 (X);
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I1 = -12345 (X);
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I2 = -23456 (X);
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I3 = -3456 (X);
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B0 = -4567 (X);
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B1 = -5678 (X);
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B2 = -6678 (X);
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B3 = -7012 (X);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0xFFFF8000;
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CHECKREG r1, 0xFFFFCFC7;
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CHECKREG r2, 0xFFFFA460;
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CHECKREG r3, 0xFFFFF280;
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CHECKREG r4, 0xFFFFEE29;
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CHECKREG r5, 0xFFFFE9D2;
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CHECKREG r6, 0xFFFFE5EA;
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CHECKREG r7, 0xFFFFE49C;
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I0 = 0x7abd (X);
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I1 = 0x7bf4 (X);
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I2 = 0x6c45 (X);
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I3 = 0x7d56 (X);
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B0 = 0x7e67 (X);
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B1 = 0x7f78 (X);
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B2 = 0x7ff9 (X);
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B3 = 0x7fff (X);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00007abd;
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CHECKREG r1, 0x00007bf4;
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CHECKREG r2, 0x00006c45;
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CHECKREG r3, 0x00007d56;
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CHECKREG r4, 0x00007e67;
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CHECKREG r5, 0x00007f78;
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CHECKREG r6, 0x00007ff9;
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CHECKREG r7, 0x00007fff;
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M0 = 0x7123 (X);
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M1 = 0x7234 (X);
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M2 = 0x7345 (X);
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M3 = 0x7456 (X);
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L0 = 0x7567 (X);
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L1 = 0x7678 (X);
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L2 = 0x7789 (X);
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L3 = 0x789a (X);
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R0 = M0;
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R1 = M1;
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R2 = M2;
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R3 = M3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x00007123;
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CHECKREG r1, 0x00007234;
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CHECKREG r2, 0x00007345;
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CHECKREG r3, 0x00007456;
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CHECKREG r4, 0x00007567;
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CHECKREG r5, 0x00007678;
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CHECKREG r6, 0x00007789;
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CHECKREG r7, 0x0000789A;
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M0 = -32768 (X);
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M1 = -123 (X);
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M2 = -234 (X);
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M3 = -345 (X);
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L0 = -456 (X);
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L1 = -567 (X);
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L2 = -667 (X);
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L3 = -701 (X);
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R0 = M0;
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R1 = M1;
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R2 = M2;
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R3 = M3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0xFFFF8000;
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CHECKREG r1, 0xFFFFFF85;
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CHECKREG r2, 0xFFFFFF16;
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CHECKREG r3, 0xFFFFFEA7;
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CHECKREG r4, 0xFFFFFE38;
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CHECKREG r5, 0xFFFFFDC9;
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CHECKREG r6, 0xFFFFFD65;
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CHECKREG r7, 0xFFFFFD43;
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M0 = 0x7aaa (X);
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M1 = 0x7bbb (X);
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M2 = 0x7ccc (X);
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M3 = 0x7ddd (X);
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L0 = 0x7eee (X);
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L1 = 0x7fa8 (X);
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L2 = 0x7fb9 (X);
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L3 = 0x7fcc (X);
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R0 = M0;
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R1 = M1;
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R2 = M2;
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R3 = M3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x00007aaa;
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CHECKREG r1, 0x00007bbb;
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CHECKREG r2, 0x00007ccc;
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CHECKREG r3, 0x00007ddd;
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CHECKREG r4, 0x00007eee;
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CHECKREG r5, 0x00007fa8;
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CHECKREG r6, 0x00007fb9;
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CHECKREG r7, 0x00007fcc;
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pass
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