167 lines
2.9 KiB
ArmAsm
167 lines
2.9 KiB
ArmAsm
//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp
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// Spec Reference: loopsetup nested inside
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS 0;
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ASTAT = r0;
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//p0 = 2;
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P1 = 3;
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P2 = 4;
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P3 = 5;
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P4 = 6;
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P5 = 7;
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SP = 8;
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FP = 9;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start1 , end1 ) LC0 = P1;
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start1: R0 += 1;
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R1 += -2;
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LSETUP ( start2 , end2 ) LC1 = P2;
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start2: R4 += 4;
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end2: R5 += -5;
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R3 += 1;
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end1: R2 += 3;
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R3 += 4;
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LSETUP ( start3 , end3 ) LC1 = P3;
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start3: R6 += 6;
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LSETUP ( start4 , end4 ) LC0 = P4 >> 1;
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start4: R0 += 1;
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R1 += -2;
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end4: R2 += 3;
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R3 += 4;
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end3: R7 += -7;
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R3 += 1;
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CHECKREG r0, 0x00000017;
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CHECKREG r1, 0xFFFFFFEC;
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CHECKREG r2, 0x00000056;
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CHECKREG r3, 0x0000004C;
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CHECKREG r4, 0x00000070;
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CHECKREG r5, 0x00000014;
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CHECKREG r6, 0x0000007E;
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CHECKREG r7, 0x0000004D;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start5 , end5 ) LC0 = P5;
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start5: R4 += 1;
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LSETUP ( start6 , end6 ) LC1 = SP >> 1;
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start6: R6 += 4;
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end6: R7 += -5;
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R3 += 6;
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end5: R5 += -2;
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R3 += 3;
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CHECKREG r0, 0x00000005;
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CHECKREG r1, 0x00000010;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x0000005D;
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CHECKREG r4, 0x00000047;
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CHECKREG r5, 0x00000042;
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CHECKREG r6, 0x000000D0;
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CHECKREG r7, 0xFFFFFFE4;
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LSETUP ( start7 , end7 ) LC0 = FP;
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start7: R4 += 4;
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end7: R5 += -5;
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R3 += 6;
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CHECKREG r0, 0x00000005;
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CHECKREG r1, 0x00000010;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000063;
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CHECKREG r4, 0x0000006B;
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CHECKREG r5, 0x00000015;
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CHECKREG r6, 0x000000D0;
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CHECKREG r7, 0xFFFFFFE4;
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P1 = 12;
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P2 = 14;
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P3 = 16;
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P4 = 18;
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P5 = 20;
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SP = 22;
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FP = 24;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start11 , end11 ) LC1 = P1;
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start11: R0 += 1;
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R1 += -1;
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LSETUP ( start15 , end15 ) LC0 = P5;
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start15: R4 += 1;
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end15: R5 += -1;
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R3 += 1;
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end11: R2 += 1;
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R3 += 1;
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LSETUP ( start13 , end13 ) LC1 = P3;
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start13: R6 += 1;
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LSETUP ( start12 , end12 ) LC0 = P2;
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start12: R4 += 1;
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end12: R5 += -1;
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R3 += 1;
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end13: R7 += -1;
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R3 += 1;
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CHECKREG r0, 0x00000011;
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CHECKREG r1, 0x00000004;
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CHECKREG r2, 0x0000002C;
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CHECKREG r3, 0x0000004E;
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CHECKREG r4, 0x00000210;
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CHECKREG r5, 0xFFFFFE80;
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CHECKREG r6, 0x00000070;
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CHECKREG r7, 0x00000060;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start14 , end14 ) LC0 = P4;
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start14: R0 += 1;
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R1 += -1;
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LSETUP ( start16 , end16 ) LC1 = SP;
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start16: R6 += 1;
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end16: R7 += -1;
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R3 += 1;
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LSETUP ( start17 , end17 ) LC1 = FP >> 1;
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start17: R4 += 1;
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end17: R5 += -1;
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R3 += 1;
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end14: R2 += 1;
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R3 += 1;
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CHECKREG r0, 0x00000017;
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CHECKREG r1, 0xFFFFFFFE;
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CHECKREG r2, 0x00000032;
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CHECKREG r3, 0x00000055;
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CHECKREG r4, 0x00000118;
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CHECKREG r5, 0xFFFFFF78;
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CHECKREG r6, 0x000001EC;
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CHECKREG r7, 0xFFFFFEE4;
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pass
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